Jun Cao

SYSTEMS AND METHODS FOR INTERFERENCE CANCELLATION

SYSTEMS AND METHODS FOR CLOCK CALIBRATION IN COMMUNICATION SYSTEMS

DUTY CYCLE CORRECTION OF PHASE INTERPOLATOR OUTPUT

CLOCK CALIBRATION FOR HIGH-SPEED SERIAL-LINK TRANSMITTERS

WIDEBAND DISTRIBUTED AMPLIFIER IN A RECEIVER

DATA-PATH ARCHITECTURE FOR ANALOG-TO-DIGITAL CONVERTERS

SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER WITH COMPARATOR PERFORMANCE CALIBRATION

SYSTEMS AND METHODS FOR INTERFERENCE CANCELLATION

SYSTEMS AND METHODS FOR IMPLEMENTING A DUAL-CORE VOLTAGE-CONTROLLED OSCILLATOR

WIDE FREQUENCY RANGE HIGH SPEED CLOCK MULTIPLEXER

Low-Voltage Reference Buffer with Wide Output Voltage and Current Range

Autonomous Synchronization Architecture for Massively Time-Interleaved Analog to Digital Converters

Low Latency Gearbox Retimer Architecture

CLOCK CALIBRATION FOR HIGH-SPEED SERIAL-LINK TRANSMITTERS

NOVEL INTEGRATED PROGRAMMABLE GAIN AMPLIFIER (PGA) AND PROTECTION CIRCUIT

METHOD AND SYSTEM FOR DIGITAL NON-LINEARITY COMPENSATION

SYSTEM AND METHOD OF GENERATING SIGNALS FOR ANALOG-DIGITAL CONVERTER (ADC) CALIBRATION

SYSTEM AND METHOD FOR PERFORMING ADAPTIVE VOLTAGE SCALING (AVS) FOR ANALOG-TO-DIGITAL CONVERTERS (ADCS)

METHOD AND SYSTEM FOR INJECTION LOCKED DIVIDER WITH FREQUENCY CALIBRATION

DISTRIBUTED PROGRAMMABLE GAIN AMPLIFIER

SYSTEM AND METHOD FOR TRANSITION AWARE BINARY SWITCHING FOR DIGITAL-TO-ANALOG CONVERTERS (DACS)

DIGITAL PRE-DISTORTION METHOD AND APPARATUS FOR A DIGITAL TO ANALOG CONVERTER

SYSTEMS AND METHODS FOR QUADRATURE DELAY CLOCK GENERATION

Systems for and methods of phase interpolation

WIDE FREQUENCY RANGE HIGH SPEED CLOCK MULTIPLEXER

Reference-ripple compensation technique for SAR ADC

SPLIT-DITHERING SCHEME IN SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER

SAMPLE AND HOLD CIRCUIT AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION

INTEGRATED TRANSIMPEDANCE AMPLIFIER WITH A DIGITAL SIGNAL PROCESSOR FOR HIGH-SPEED OPTICAL RECEIVERS

Digital pre-distortion method and apparatus for a digital to analog converter

System and apparatus for on-substrate circuit configured to operate as transformer

SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER WITH REDUCED DATA PATH LATENCY

Configurable prime number divider using multi-phase clocks

Adaptive alignment of sample clocks within analog-to-digital converters

Novel Integrated Programmable Gain Amplifier (PGA) and Protection Circuit

Super source follower with feedback resistor and inductive peaking

Systems for and methods of wideband distributed amplification

Successive approximation register analog to digital converter having adaptive current or voltage parameter adjustments

Successive approximation register analog to digital converter with reduced data path latency

System and method for offset calibration in a successive approximation analog to digital converter

Systems for and methods of fractional frequency division

Integrated transimpedance amplifier with a digital signal processor for high-speed optical receivers

Variation tolerant linear phase-interpolator

SYNCHRONIZATION OF DEVICES WITH A GAPPED REFERENCE CLOCK

Power supply generation for transmitter

Systems for and methods of fractional frequency division

Quadrature delay locked loops

High-speed transmitter including a multiplexer using multi-phase clocks

Phase and frequency detection method and circuit

Pulse amplifier

Quadrature delay locked loops

Pre-driver peaking technique for high-speed DACs

COUPLED T-COIL

BOOTSTRAPPED HIGH-SPEED SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER

Clock skew suppression for time-interleaved clocks

Long-distance high-speed data and clock transmission

Multiplexer circuit for a digital to analog converter

Multi-segmented all logic DAC

Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration

Time interleaving structure for a multi-lane analog-to-digital converter (ADC)

High-speed, low-power reconfigurable voltage-mode DAC-driver

Long-distance high-speed data and clock transmission

Phase alignment architecture for ultra high-speed data path

Process Mitigated Clock Skew Adjustment

Process mitigated clock skew adjustment

Multilane serdes clock and data skew alignment for multi-standard support

Phase adjustment scheme for time-interleaved ADCS

High speed level shifter with amplitude servo loop

Transceiver including a high latency communication channel and a low latency communication channel

Adaptive harmonic distortion suppression in an amplifier utilizing negative gain

Clock generator for use in a time-interleaved ADC and methods for use therewith

Multilane SERDES clock and data skew alignment for multi-standard support

Transceiver including a high latency communication channel and a low latency communication channel

Resonant clock amplifier with a digitally tunable delay

Distributed resonate clock driver

Multi-protocol communications receiver with shared analog front-end

Amplifier bandwidth extension for high-speed tranceivers

Compact high-speed mixed-signal interface

Low latency high bandwidth CDR architecture

Amplifier bandwidth extension for high-speed tranceivers

Symmetrical clock distribution in multi-stage high speed data conversion circuits

MULTIPLEXER CIRCUIT

Resonant clock amplifier with a digitally tunable delay

Multiple gigahertz clock-data alignment scheme

Summer block for a decision feedback equalizer

Multi-channel multi-protocol transceiver with independent channel configuration using single frequency reference clock source

Multi-protocol communications receiver with shared analog front-end

High speed low power multiple standard and supply output driver

Electronic dispersion compensation within optical communications using reconstruction

Symmetrical clock distribution in multi-stage high speed data conversion circuits

Apparatus and method for analog-to-digital converter calibration

Signal delay structure in high speed bit stream demultiplexer

Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth

Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading

Signal delay structure in high speed bit stream demultiplexer

Hybrid High-Speed/Low-Speed Output Latch in 10 GBPS Interface with Half Rate Clock

Variable gain amplifier and method for achieving variable gain amplification with high bandwidth and linearity

Symmetrical clock distribution in multi-stage high speed data conversion circuits

Apparatus and method for analog-to-digital converter calibration

Hybrid high-speed/low-speed output latch in 10 GBPS interface with half rate clock