Adam B. Eldredge

Cascaded PLL for reducing low-frequency drift in holdover mode

Interpolative divider linearity enhancement techniques

Higher-order phase noise modulator to reduce spurs and quantization noise

Mutual inductance circuits

Sigma-delta modulation with reduction of spurs using a dither signal

PLL using interpolative divider as digitally controlled oscillator

Calibrating a phase detector and analog-to-digital converter offset and gain

Robust false locking prevention in referenceless frequency acquisition

Input buffer

Data cleaning with an asynchronous reference clock

Reducing phase offsets in a phase detector

Calibrating a phase detector and analog-to-digital converter offset and gain

Determining signal quality and selecting a slice level via a forbidden zone