David R. Terry

Register file write using pointers

Implementing write ports in register-file array cell

Operation of a multi-slice processor implementing a hardware level transfer of an execution thread

Issue queue snooping for asynchronous flush and restore of distributed history buffer

Asynchronous flush and restore of distributed history buffer

Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor

Multi-level history buffer for transaction memory in a microprocessor

Operation of a multi-slice processor with selective producer instruction types

Operation of a multi-slice processor with selective producer instruction types

OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING INSTRUCTION FUSION

ECC scrubbing method in a multi-slice microprocessor

Reducing power consumption in a multi-slice computer processor

Reducing power consumption in a multi-slice computer processor

ECC scrubbing in a multi-slice microprocessor

Direct register restore mechanism for distributed history buffers

In-pipe error scrubbing within a processor core

Operation of a multi-slice processor implementing a hardware level transfer of an execution thread

Preventing premature reads from a general purpose register

Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor

Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction

Operation of a multi-slice processor with selective producer instruction types

Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction

Operation of a multi-slice processor with reduced flush and restore latency

Operation of a multi-slice processor with selective producer instruction types

Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor

Operation of a multi-slice processor with reduced flush and restore latency

Reducing power consumption in a multi-slice computer processor

Reducing power consumption in a multi-slice computer processor

Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture

Method and apparatus for managing a speculative transaction in a processing unit

Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions

Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data

METHOD AND APPARATUS FOR WRITING A PORTION OF A REGISTER IN A MICROPROCESSOR

Partial ECC mechanism for a byte-write capable register

Generating ECC values for byte-write capable registers

Partial ECC handling for a byte-write capable register

Generating ECC values for byte-write capable registers

Parity protection of a register

Split-level history buffer in a computer processing unit

Split-level history buffer in a computer processing unit

Split-level history buffer in a computer processing unit

Split-level history buffer in a computer processing unit

Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor

Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor

Distributed history buffer flush and restore handling in a parallel slice design

Distributed history buffer flush and restore handling in a parallel slice design

History buffer for multiple-field registers