Daniel M. Dreps

Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module

High-speed voltage clamp for unterminated transmission lines

Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module

Redundant clock switch

Phase rotator

Adjustable phase shifter

MULTICOMPONENT MODULE DESIGN AND FABRICATION

Redundant voltage delivery with active cables

Architecture with micro-controller and high-speed active cables

PCB with substrate integrated waveguides using multi-band monopole antenna feeds for high speed communication

Vertically transitioning between substrate integrated waveguides (SIWs) within a multilayered printed circuit board (PCB)

Level shifting between interconnected chips having different voltage potentials

Oscillator failure detection circuit

Versatile signal detector circuit using common mode shift with all-pass characteristics

System, method and computer program product for data transfer management

Reconfigurble CPU/GPU interconnect to mitigate power/thermal throttling

Embedded filtering in PCB integrated ultra high speed dielectric waveguides using photonic band gap structures

Multilayer ceramic electronic package with modulated mesh topology and alternating rods

Multilayer ceramic electronic package with modulated mesh topology

Reconfigurable network infrastructure

Overvoltage protection circuit

Implementing high-speed signaling via dedicated printed circuit-board media

System, method and computer program product for data transfer management

Reduction of crosstalk between dielectric waveguides using split ring resonators

Communication system having a multi-layer PCB including a dielectric waveguide layer with a core and cladding directly contacting ground planes

Pre-transmission data reordering for a serial interface

Overvoltage protection circuit

Staged power on/off sequence at the I/O phy level in an interchip interface

Power reduction in a parallel data communications interface using clock resynchronization

Distributed serialized data buffer and a memory module for a cascadable and extended memory subsystem

Dynamic link repair from lane failure with minimal link down-time while sparing fault channels

Dynamic link repair from lane failure with minimal link-down time while sparing fault channels

Open-loop quadrature clock corrector and generator

Clock forwarding over optics

Impedance matching system for DDR memory

Frequency-domain high-speed bus signal integrity compliance model

Frequency-domain high-speed bus signal integrity compliance model

Frequency-domain high-speed bus signal integrity compliance model

Frequency-domain high-speed bus signal integrity compliance model

Power reduction in a parallel data communications interface using clock resynchronization

Phased locked loop with multiple voltage controlled oscillators

Interface clock frequency switching using a computed insertion delay

Efficient calibration of a low power parallel data communications channel

Dynamic optical channel sparing in an industry standard input/output subsystem

Dynamic optical channel sparing in an industry standard input/output subsystem

Overvoltage protection circuit

Packaging for eight-socket one-hop SMP topology

Packaging for eight-socket one-hop SMP topology

Power aware equalization in a serial communications link

High speed differential wiring in glass ceramic MCMS

High speed differential wiring in glass ceramic MCMS

Overvoltage protection circuit

Overvoltage protection circuit

Digital phase detector with zero phase offset

Systems and methods for signal detection

Systems for signal detection

Low latency data transfer between clock domains operated in various synchronization modes

Implementing high-speed signaling via dedicated printed circuit-board media

Efficient calibration of a low power parallel data communications channel

Fault tolerant parallel receiver interface with receiver redundancy

Digital phase detector with zero phase offset

Strobe offset in bidirectional memory strobe configurations

Multi-use physical architecture

Redundant clock channel for high reliability connectors

Implementing high-speed signaling via dedicated printed circuit-board media

Strobe offset in bidirectional memory strobe configurations

Self-healing chip-to-chip interface

Advanced memory device having reduced power and improved performance

Configurable pre-emphasis driver with selective constant and adjustable output impedance modes

Physical interface macros (PHYS) supporting heterogeneous electrical properties

Supporting multiple high bandwidth I/O controllers on a single chip

Self-healing chip-to-chip interface

Variable input voltage regulator

Controllable voltage reference driver for a memory system

Enhanced microprocessor interconnect with bit shadowing

Bit shadowing in a memory system

MICROPROCESSOR INTERFACE WITH DYNAMIC SEGMENT SPARING AND REPAIR

Dynamic segment sparing and repair in a memory system

Controlling for variable impedance and voltage in a memory system

Communications system via data scrambling and associated methods

Phase interpolator system and associated methods

On-chip high frequency power supply noise sensor

Memory systems for automated computing machinery

System for providing open-loop quadrature clock generation

Multimodal memory controllers

Multimodal memory controllers

276-pin buffered memory module with enhanced fault tolerance

276-pin buffered memory module with enhanced fault tolerance

Multimodal Memory Controllers

Signal history controlled slew-rate transmission method and bus interface transmitter

Signal history controlled slew-rate transmission method and bus interface transmitter

Memory systems for automated computing machinery

276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment

276-pin buffered memory module with enhanced fault tolerance

Reduced cross-talk signaling circuit and method

Elastic interface de-skew mechanism

Dynamic recalibration mechanism for elastic interface

Peaking transmission line receiver for logic signals

Programmable delay element

Circuit for optimizing the duty cycle of a received clock transmitted over a transmission line