Chih-Ching WANG

MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR STRUCTURE WITH BACKSIDE CONTACTS

INNER SPACERS FOR MULTI-GATE TRANSISTORS AND MANUFACTURING METHOD THEREOF

REDUCTION OF SIZE OF EDGE CELL REGION IN MEMORY DEVICES

SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF

Gate All Around Transistor Device and Fabrication Methods Thereof

MULTI-GATE DEVICES AND FABRICATING THE SAME WITH ETCH RATE MODULATION

SOURCE/DRAIN FEATURES WITH IMPROVED STRAIN PROPERTIES

Channel Configuration for Improving Multigate Device Performance and Method of Fabrication Thereof

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR STRUCTURE WITH BACKSIDE CONTACTS

DIELECTRIC FIN STRUCTURE

SEMICONDUCTOR FABRICATION PROCESSES FOR DEFECT REDUCTION

INNER SPACERS FOR MULTI-GATE TRANSISTORS AND MANUFACTURING METHOD THEREOF

REDUCTION OF SIZE OF EDGE CELL REGION IN MEMORY DEVICES

Multi-gate devices and fabricating the same with etch rate modulation

MULTI-GATE DEVICES WITH MULTI-LAYER INNER SPACERS AND FABRICATION METHODS THEREOF

SEMICONDUCTOR DEVICE WITH BACKSIDE INTERCONNECTION AND METHOD FOR FORMING THE SAME

MULTI-GATE DEVICE INNER SPACER AND METHODS THEREOF

SEMICONDUCTOR DEVICE STRUCTURE WITH NANOSTRUCTURE AND METHOD FOR FORMING THE SAME

Source/drain features with improved strain properties

SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF

Dielectric fin structure

Channel configurations with stacked segments for gate-all-around based devices and methods of fabrication thereof

Gate All Around Transistor Device and Fabrication Methods Thereof

SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF

Source/drain features with improved strain properties

Dielectric fin structure

Source/drain silicide for multigate device performance and method of fabricating thereof

Multi-gate devices and fabricating the same with etch rate modulation

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Dielectric fin structure

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Multi-gate devices and fabricating the same with etch rate modulation

Channel configuration for improving multigate device performance and method of fabrication thereof

Multi-gate devices with multi-layer inner spacers and fabrication methods thereof

Gate all around transistor device and fabrication methods thereof

Series-connected transistor structure