William R. Mark

ENCODER NEURAL NETWORKS WITH POWER CONSTRAINED LATENT REPRESENTATIONS

Convolutional neural network on programmable two dimensional image processor

Macro I/O unit for image processor

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

COMPILER TECHNIQUES FOR MAPPING PROGRAM CODE TO A HIGH PERFORMANCE, POWER EFFICIENT, PROGRAMMABLE IMAGE PROCESSING HARDWARE PLATFORM

Architecture for high performance, power efficient, programmable image processing

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Block Operations For An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register

Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register

Convolutional neural network on programmable two dimensional image processor

Convolutional neural network on programmable two dimensional image processor

Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform

Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform

Architecture for high performance, power efficient, programmable image processing

System and method for interfacing graphics program modules