Dublin, California
United States
32
2026-02-05
The entities that hold a legal rights for patent applications filed by inventor SANKARAN Jagadeesh:
Jagadeesh SANKARAN from Dublin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
COORDINATING PROCESSING TASKS BETWEEN ONE-DIMENSIONAL PROCESSING ENGINES AND TWO-DIMENSIONAL PROCESSING ENGINES
#2 | 2026-02-05SYSTEMS AND METHODS FOR PERFORMING INTER-ACCELERATOR DATA TRANSFERS
#3 | 2026-02-05SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS DATA TRANSFERS
#4 | 2026-02-05SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS DATA TRANSFERS
#5 | 2026-02-05PROCESSING DATA USING ACCELERATORS WITH MULTI-FRAME SUPPORT
#6 | 2026-02-05SYSTEMS AND METHODS FOR PROCESSING DATA BASED AT LEAST ON RANDOM REGIONS IN A FRAME
#7 | 2026-02-05LOAD AND STORE MEMORY ARCHITECTURE
#8 | 2026-02-05PROCESSING DATA USING ACCELERATORS IN A SYSTEM ON A CHIP
#9 | 2025-03-27USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SYSTEM ON A CHIP
#10 | 2024-08-08OBJECT DETECTION USING IMAGE ALIGNMENT FOR AUTONOMOUS MACHINE APPLICATIONS
#11 | 2024-04-25USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM FOR FEATURE TRACKING OPERATIONS IN A SYSTEM ON A CHIP
#12 | 2024-02-08ACCELERATING TABLE LOOKUPS USING A DECOUPLED LOOKUP TABLE ACCELERATOR IN A SYSTEM ON A CHIP
#13 | 2023-06-15Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip
#14 | 2023-05-18Hardware accelerated anomaly detection using a min/max collector in a system on a chip
#15 | 2023-04-27HYBRID SOLUTION FOR STEREO IMAGING
#16 | 2023-04-27Built-in self-test for a programmable vision accelerator of a system on a chip
#17 | 2023-04-20Using per memory bank load caches for reducing power use in a system on a chip
#18 | 2023-04-13Using a hardware sequencer in a direct memory access system of a system on a chip
#19 | 2023-03-09Performing load and permute with a single instruction in a system on a chip
#20 | 2023-02-16Performing multiple point table lookups in a single cycle in a system on chip
#21 | 2023-02-16Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip
#22 | 2023-02-16SIMD DATA PATH ORGANIZATION TO INCREASE PROCESSING THROUGHPUT IN A SYSTEM ON A CHIP
#23 | 2023-02-16Reduced memory write requirements in a system on a chip using automatic store predication
#24 | 2023-02-16Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip
#25 | 2023-02-16Using per memory bank load caches for reducing power use in a system on a chip
#26 | 2023-02-16Hardware accelerated anomaly detection using a min/max collector in a system on a chip
#27 | 2023-02-09Performing load and store operations of 2D arrays in a single cycle in a system on a chip
#28 | 2023-02-09OFFLOADING PROCESSING TASKS TO DECOUPLED ACCELERATORS FOR INCREASING PERFORMANCE IN A SYSTEM ON A CHIP
#29 | 2023-02-09Using a hardware sequencer in a direct memory access system of a system on a chip
#30 | 2023-02-09Built-in self-test for a programmable vision accelerator of a system on a chip
#31 | 2021-08-26Object detection using image alignment for autonomous machine applications
#32 | 2016-11-03Programmable vision accelerator
1699822 ⎘