Inventor profile of:

JAY R. HERRING

City:

POUGHKEEPSIE, New York

Country:

United States

Published Applications:

21

Last publication date:

2013-03-28

Top Assignees for applications by JAY R. HERRING

The entities that hold a legal rights for patent applications filed by inventor HERRING JAY R.:

Recent patent applications by HERRING JAY R.

JAY R. HERRING from POUGHKEEPSIE, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-03-28
US20130080825A1
Physics

Cable redundancy and failover for multi-lane PCI express IO interconnections

#2 | 2013-03-28
US20130080678A1
Physics

Cable redundancy and failover for multi-lane PCI express IO interconnections

#3 | 2012-06-07
US20120144230A1
Physics

Cable redundancy and failover for multi-lane PCI express IO interconnections

#4 | 2012-06-07
US20120144087A1
Physics

Cable redundancy and failover for multi-lane PCI express IO interconnections

#5 | 2008-12-18
US20080313514A1
Physics

On-Chip AC self-test controller

#6 | 2008-08-28
US20080205278A1
Electricity

Method for actively managing central queue buffer allocation

#7 | 2007-12-06
US20070280248A1
Electricity

Method for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables

#8 | 2007-10-25
US20070248096A1
Electricity

System and program product for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables

#9 | 2007-10-18
US20070245195A1
Physics

Method, system and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit

#10 | 2007-10-11
US20070240025A1
Physics

Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit

#11 | 2007-03-06
US10185028
-

Priority arbitration mechanism

#12 | 2006-10-26
US20060242509A1
Physics

Method and system for an on-chip AC self-test controller

#13 | 2006-06-06
US10131554
-

Method and system for an on-chip AC self-test controller

#14 | 2006-05-18
US20060107149A1
Physics

Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit

#15 | 2006-05-04
US20060095820A1
Physics

Method, system, and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit

#16 | 2005-10-13
US20050226145A1
Electricity

System and program product for actively managing central queue buffer allocation

#17 | 2005-07-28
US20050166104A1
Physics

Simultaneous AC logic self-test of multiple clock domains

#18 | 2005-07-14
US20050155003A1
Physics

Scalable logic self-test configuration for multiple chips

#19 | 2005-07-07
US20050149600A1
Electricity

Method, system and program product for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables

#20 | 2005-04-14
US20050080933A1
Electricity

Master-slave adapter

#21 | 2005-04-14
US20050078559A1
Electricity

Global recovery for time of day synchronization

InventorID:

170104 ⎘