Inventor profile of:

Mysore S. Srinivas

City:

Austin, Texas

Country:

United States

Published Applications:

50

Last publication date:

2024-06-13

Top Assignees for applications by Mysore S. Srinivas

The entities that hold a legal rights for patent applications filed by inventor Srinivas Mysore S.:

Recent patent applications by Srinivas Mysore S.

Mysore S. Srinivas from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-06-13
US20240192851A1
Physics

SHARED MEMORY AUTONOMIC SEGMENT SIZE PROMOTION IN A PAGED-SEGMENTED OPERATING SYSTEM

#2 | 2019-02-28
US20190065280A1
Physics

Hybrid virtual machine configuration management

#3 | 2018-02-01
US20180032343A1
Physics

Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor

#4 | 2017-10-26
US20170308468A1
Physics

PERFORMANCE-DRIVEN CACHE LINE MEMORY ACCESS

#5 | 2017-06-15
US20170168833A1
Physics

INSTRUCTION WEIGHTING FOR PERFORMANCE PROFILING IN A GROUP DISPATCH PROCESSOR

#6 | 2017-06-15
US20170168832A1
Physics

INSTRUCTION WEIGHTING FOR PERFORMANCE PROFILING IN A GROUP DISPATCH PROCESSOR

#7 | 2016-03-24
US20160085595A1
Physics

Hybrid virtual machine configuration management

#8 | 2016-01-21
US20160019095A1
Physics

Assigning a first portion of physical computing resources to a first logical partition and a second portion of the physical computing resources to a second logical portion

#9 | 2014-09-11
US20140258642A1
Physics

Dynamic prioritization of cache access

#10 | 2014-06-19
US20140173597A1
Physics

Hybrid virtual machine configuration management

#11 | 2014-06-19
US20140173595A1
Physics

Hybrid virtual machine configuration management

#12 | 2014-05-22
US20140143465A1
Physics

Offloading input/output (I/O) completion operations

#13 | 2014-05-22
US20140143458A1
Physics

Offloading input/output (I/O) completion operations

#14 | 2014-04-03
US20140095796A1
Physics

Performance-driven cache line memory access

#15 | 2014-04-03
US20140095791A1
Physics

Performance-driven cache line memory access

#16 | 2013-08-22
US20130218892A1
Physics

Hybrid storage subsystem with mixed placement of file contents

#17 | 2013-06-13
US20130151788A1
Physics

Dynamic prioritization of cache access

#18 | 2013-06-13
US20130151784A1
Physics

Dynamic prioritization of cache access

#19 | 2013-05-02
US20130111136A1
Physics

Variable cache line size management

#20 | 2013-05-02
US20130111135A1
Physics

Variable cache line size management

#21 | 2013-03-28
US20130080712A1
Physics

Non-uniform memory access (NUMA) enhancements for shared logical partitions

#22 | 2012-11-29
US20120304002A1
Physics

Managing rollback in a transactional memory environment

#23 | 2012-11-29
US20120303938A1
Physics

Performance in predicting branches

#24 | 2012-11-29
US20120303591A1
Physics

Managing rollback in a transactional memory environment

#25 | 2012-10-11
US20120260257A1
Physics

Computer program product for scheduling ready threads in a multiprocessor computer based on an interrupt mask flag value associated with a thread and a current processor priority register value

#26 | 2012-08-23
US20120216214A1
Physics

Mixed operating performance modes including a shared cache mode

#27 | 2012-08-23
US20120216212A1
Physics

Dynamically assigning a portion of physical computing resource to logical partitions based on characteristics of executing logical partitions

#28 | 2012-07-12
US20120180052A1
Physics

Managing migration of a prefetch stream from one processor core to another processor core

#29 | 2012-07-12
US20120179873A1
Physics

Performance of emerging applications in a virtualized environment using transient instruction streams

#30 | 2012-05-17
US20120124299A1
Physics

System, method and computer program product for extending a cache using processor registers

#31 | 2012-04-26
US20120102499A1
Physics

Optimizing the performance of hybrid CPU systems based upon the thread type of applications to be run on the CPUs

#32 | 2012-04-19
US20120096241A1
Physics

Performance of emerging applications in a virtualized environment using transient instruction streams

#33 | 2012-04-19
US20120096240A1
Physics

Managing migration of a prefetch stream from one processor core to another processor core

#34 | 2011-12-29
US20110320573A1
Physics

Application server for mainframe computer systems

#35 | 2011-06-30
US20110161979A1
Physics

Mixed operating performance modes including a shared cache mode

#36 | 2011-06-23
US20110153931A1
Physics

Hybrid storage subsystem with mixed placement of file contents

#37 | 2011-06-16
US20110145505A1
Physics

Assigning cache priorities to virtual/logical processors and partitioning a cache according to such priorities

#38 | 2011-04-21
US20110093861A1
Physics

Dynamically assigning a portion of physical computing resource to logical partitions based on characteristics of executing logical partitions

#39 | 2010-09-02
US20100223622A1
Physics

Non-uniform memory access (NUMA) enhancements for shared logical partitions

#40 | 2009-10-08
US20090252057A1
Electricity

WIRELESS SERVICE PROCESSOR CONNECTIONS

#41 | 2008-10-16
US20080256302A1
Physics

Programmable data prefetching

#42 | 2008-10-02
US20080244568A1
Physics

Capturing hardware statistics for partitions to enable dispatching and scheduling efficiency

#43 | 2008-10-02
US20080244215A1
Physics

Workload management in virtualized data processing environment

#44 | 2008-10-02
US20080244214A1
Physics

Workload management in virtualized data processing environment

#45 | 2008-10-02
US20080244213A1
Physics

Workload management in virtualized data processing environment

#46 | 2008-07-31
US20080184246A1
Physics

Scheduling threads in a multiprocessor computer

#47 | 2008-07-10
US20080165800A1
Physics

METHOD AND APPARATUS TO PROVIDE DYNAMIC COST OF CONTEXT SWITCH TO APPLICATION FOR PERFORMANCE OPTIMIZATION

#48 | 2007-05-03
US20070101333A1
Physics

System and method of arbitrating access of threads to shared resources within a data processing system

#49 | 2007-03-15
US20070061810A1
Physics

Synchronizing access to a shared resource utilizing selective locking

#50 | 2005-01-18
US9779369
-

Method and system for managing lock contention in a computer system

InventorID:

170179 ⎘