Young-Su KWON

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE COMPRISING SAME

PHYSICAL LAYER OF HIGH-SPEED MEMORY AND READ TRAINING METHOD OF HIGH-SPEED MEMORY

HIGH-SPEED I/O CIRCUIT FOR DIE-TO-DIE INTERCONNECT FOR SUPPRESSING OVERSHOOT AND UNDERSHOOT

REFERENCE VOLTAGE CALIBRATION APPARATUS IN MEMORY INTERFACE

METHOD FOR SUPPORTING CACHE COHERENCY BASED ON VIRTUAL ADDRESSES FOR ARTIFICIAL INTELLIGENCE PROCESSOR HAVING LARGE ON-CHIP MEMORY AND APPARATUS FOR THE SAME

Duty cycle monitoring method and apparatus for memory interface

DEVICE AND METHOD FOR CALIBRATING REFERENCE VOLTAGE

APPARATUS FOR RECEIVING DATA FROM MEMORY

METHOD AND APPARATUS FOR FLOATING-POINT DATA TYPE MATRIX MULTIPLICATION BASED ON OUTER PRODUCT

METHOD AND APPARATUS FOR ALLOCATING TASK IN MULTI PROCESSOR

Digital clock and data recovery circuit and feedback loop circuit including the same

Apparatus and method for receiving strobe signal

POWER SYSTEM BASED ON BETA SOURCE AND METHOD FOR OPERATING THE SAME

Memory interface device

AI ACCELERATOR, CACHE MEMORY AND METHOD OF OPERATING CACHE MEMORY USING THE SAME

CIRCUIT FOR IMPLEMENTING SIMPLIFIED SIGMOID FUNCTION AND NEUROMORPHIC PROCESSOR INCLUDING THE CIRCUIT

Host apparatus, heterogeneous system architecture device, and heterogeneous system based on unified virtual memory

SYSTOLIC ARRAY PROCESSOR AND OPERATING METHOD OF SYSTOLIC ARRAY PROCESSOR

Parallel processor, address generator of parallel processor, and electronic device including parallel processor

Receiving circuit to process low-voltage signal with hysteresis

Cache for artificial intelligence processor

Electronic device for encoding event indicated by spatial-temporal input signals and operating method thereof

NEURAL NETWORK ACCELERATOR WITH SYSTOLIC ARRAY STRUCTURE

Image recognition processor including functional safety processor core and operation method thereof

Processor for detecting and preventing recognition error

Neural network system including data moving controller

Image sensor and method for extracting edge of image based on amplitudes of signals output from pixels

Processing element and operating method thereof in neural network

NEURAL NETWORK COMPUTING DEVICE AND OPERATION METHOD THEREOF

APPARATUS FOR PROCESSING CONVOLUTIONAL NEURAL NETWORK USING SYSTOLIC ARRAY AND METHOD THEREOF

METHOD AND APPARATUS FOR GENERATING ADDRESS OF DATA OF ARTIFICIAL NEURAL NETWORK

Reorganizable data processing array for neural network computing

FAULT TOLERANT NETWORK ON-CHIP

Semiconductor system including fault manager

Neural network accelerator including bidirectional processing element array

CONVOLUTION CIRCUIT, APPLICATION PROCESSOR INCLUDING THE SAME, AND OPERATING METHOD THEREOF

Multi-core processor and operation method thereof

Can controller and data transmission method using the same

Multi-core processor and cache management method thereof

Processor system and fault detection method thereof

Cache memory and operation method thereof

Cache memory device and operating method thereof

Ultra low voltage digital circuit and operation method thereof

Method and apparatus for injecting fault and analyzing fault tolerance

Apparatus and method for recovering functionality of central processing unit core

Apparatus and method for controlling level 0 cache

Cache memory with fault tolerance

Failure recovery apparatus of digital logic circuit and method thereof

Cache control device having fault-tolerant function and method of operating the same

Apparatus for error simulation and method thereof

Apparatus and method for multicore emulation based on dynamic context switching

Recoverable and fault-tolerant CPU core and control method thereof

Cache control apparatus and method

CACHE CONTROL APPARATUS AND METHOD

METHOD FOR CONTROLLING CACHE MEMORY AND APPARATUS FOR THE SAME

Method and apparatus for controlling operation voltage of processor core, and processor system including the same

PROCESSOR CAPABLE OF DETECTING FAULT AND METHOD OF DETECTING FAULT OF PROCESSOR CORE USING THE SAME

DUAL-MODE INSTRUCTION FETCHING APPARATUS AND METHOD

PROCESSOR USING BRANCH INSTRUCTION EXECUTION CACHE AND METHOD OF OPERATING THE SAME

Processor and instruction processing method in processor

ENERGY TILE PROCESSOR

Vector processing of different instructions selected by each unit from multiple instruction group based on instruction predicate and previous result comparison

Core cluster, energy scalable vector processing apparatus and method of vector processing including the same

Accessing value for local variable from function call stack upon offset matching with instruction extracted stack pointer offset or from cache

Apparatus and method for reducing memory access conflict

Method and apparatus for data transmission between processors using memory remapping

Apparatus, method and data processing element for efficient parallel processing of multimedia data