Miles Robert DOOLEY

Transaction and Request Buffers for Cache Miss Handling

Window-Based Memory Dependency Predictor

Static Instruction Caching in a Coprocessor Architecture

PROCESSOR WITH ONE OR MORE PROGRESSIVE CONSERVATIVE EXECUTION MODES

Static instruction caching in a coprocessor architecture

Controlling data allocation to storage circuitry

Pre-staged instruction registers for variable length instruction set machine

Pre-staged instruction registers for variable length instruction set machine

Controlling access requests of request nodes

Merging memory ordering tracking information for issued load instructions

Correlated addresses and prefetching

Multiple stride prefetching

Storage circuitry request tracking

Apparatus and method for efficient utilisation of an address translation cache

Cache storage

Eviction control for an address translation cache

Apparatus and method for maintaining address translation data within an address translation cache

Queuing memory access requests

Tracking the content of a cache using a way tracker having entries with a cache miss indicator

Method for detecting address match in a deeply pipelined processor design

Adaptive data prefetch

Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor

Method, apparatus and program product for enhancing performance of an in-order processor with long stalls

Method for detecting address match in a deeply pipelined processor design