Jericho, Vermont
United States
42
2016-03-10
The entities that hold a legal rights for patent applications filed by inventor DUNN James S.:
James S. DUNN from Jericho, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Dielectric region in a bulk silicon substrate providing a high-Q passive resonator
#2 | 2015-12-17Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming
#3 | 2015-12-10Dielectric region in a bulk silicon substrate providing a high-Q passive resonator
#4 | 2015-10-22Base profile of self-aligned bipolar transistors for power amplifier applications
#5 | 2015-09-10Method for making a dielectric region in a bulk silicon substrate providing a high-Q passive resonator
#6 | 2015-07-23Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures
#7 | 2015-07-09Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming
#8 | 2015-04-23Base profile of self-aligned bipolar transistors for power amplifier applications
#9 | 2015-02-19Trench isolation for bipolar junction transistors in BiCMOS technology
#10 | 2014-08-07Trench isolation for bipolar junction transistors in BiCMOS technology
#11 | 2014-07-31Forming structures on resistive substrates
#12 | 2014-07-31Flattened substrate surface for substrate bonding
#13 | 2014-06-05Tapered via and MIM capacitor
#14 | 2014-03-06Integrated circuit structure having air-gap trench isolation and related design structure
#15 | 2013-10-03Integrated circuit structure having air-gap trench isolation and related design structure
#16 | 2013-08-22Low harmonic RF switch in SOI
#17 | 2013-06-06Forming structures on resistive substrates
#18 | 2013-05-02Flattened substrate surface for substrate bonding
#19 | 2013-04-04Method of manufacturing complimentary metal-insulator-metal (MIM) capacitors
#20 | 2012-11-01Tapered via and MIM capacitor
#21 | 2012-10-18Heterojunction bipolar transistors and methods of manufacture
#22 | 2012-07-26Heterojunction bipolar transistors and methods of manufacture
#23 | 2012-07-26Complimentary metal-insulator-metal (MIM) capacitors and method of manufacture
#24 | 2012-02-16Low harmonic RF switch in SOI
#25 | 2011-02-17Heterojunction bipolar transistors and methods of manufacture
#26 | 2011-02-10Method of manufacturing complimentary metal-insulator-metal (MIM) capacitors
#27 | 2011-02-10Complimentary metal-insulator-metal (MIM) capacitors and method of manufacture
#28 | 2009-01-01Selectable device options for characterizing semiconductor devices
#29 | 2008-01-17Structure and method for performance improvement in vertical bipolar transistors
#30 | 2007-11-15Method to build self-aligned NPN in advanced BiCMOS technology
#31 | 2007-08-30Structure for performance improvement in vertical bipolar transistors
#32 | 2006-11-09Structure and method for performance improvement in vertical bipolar transistors
#33 | 2006-07-20Semiconductor device and method having multiple subcollectors formed on a common wafer
#34 | 2006-06-20Semiconductor device and method having multiple subcollectors formed on a common wafer
#35 | 2006-04-20Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same
#36 | 2006-03-23Method to build self-aligned NPN in advanced BiCMOS technology
#37 | 2005-11-03Varactors for CMOS and BiCMOS technologies
#38 | 2005-06-14Method to fabricate high-performance NPN transistors in a BiCMOS process
#39 | 2005-05-31Diffused extrinsic base and method for fabrication
#40 | 2005-05-10Varactors for CMOS and BiCMOS technologies
#41 | 2005-03-22Diffused extrinsic base and method for fabrication
#42 | 2005-03-03Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same
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