David Strong

MECHANISM TO PROTECT A PROCESSOR’S SECURITY MODEL WHILE ALLOWING TRADITIONAL UNSAFE PRACTICES WITHIN A BOUNDED MEMORY RANGE

OPAQUE ADDRESSES IN A SECURE MIGRATABLE ARCHITECTURE (SMART) PROCESSOR

SOFTWARE REMEDIATION USING PARALLEL CODE FRAGMENTS

PARALLEL CODE FRAGMENTS WITH FOREIGN CODE

WORKLOAD REALLOCATION IN HIERARCHICAL MEMORY ARCHITECTURES

System and method for responsive process security classification and optimization

SYSTEM AND METHOD ENABLING SOFTWARE-CONTROLLED PROCESSOR CUSTOMIZATION FOR WORKLOAD OPTIMIZATION

System and method for the creation and provision of execution virtual context information

System and method for securely debugging across multiple execution contexts

SYSTEM AND METHOD FOR SHARED REGISTER CONTENT INFORMATION

System and method for the detection of processing hot-spots

SYSTEM AND METHOD FOR THE GENERATION AND STORAGE OF EXECUTION TRACING INFORMATION

Feature set selection using parallel code fragments in executable code

PERFORMANCE OPTIMIZATION OF CLOSE CODE

DEFINING AND ACCESSING DYNAMIC REGISTERS IN A VIRTUAL MULTI-PROCESSOR SYSTEM

MULTI-PROCESSOR SYSTEM AND METHOD ENABLING CONCURRENT MULTI-PROCESSING UTILIZING DISCRETE COMPONENT PROCESSOR ELEMENTS

Virtual processor system and method utilizing discrete component elements

MULTI-PROCESSOR SYSTEM AND METHOD UTILIZING DISCRETE COMPONENT PROCESSOR ELEMENTS

DEFINING AND ACCESSING DYNAMIC REGISTERS IN A MULTI-PROCESSOR SYSTEM

DEFINING AND ACCESSING DYNAMIC REGISTERS IN A PROCESSOR SYSTEM

DEFINING AND ACCESSING DYNAMIC REGISTERS IN A VIRTUAL PROCESSOR SYSTEM

MESH NETWORKS FOR DISASTER RELIEF

Secure migratable architecture having improved performance features

Secure migratable architecture having security features

MEMORY MANAGEMENT WITHIN SECURE MIGRATABLE ARCHITECTURE

Secure migratable architecture having improved performance features

Secure migratable architecture having high availability

Streamlined execution of emulated code using block-based translation mode