Kirk D. Peterson

PROCESSOR CHIP TIMING ADJUSTMENT ENHANCEMENT

MULTICOMPONENT MODULE DESIGN AND FABRICATION

Predetermining separate thermal control points for chips of a multi-chip module

Microchip level shared array repair

Performance-screen ring oscillator with switchable features

Contacts having a geometry to reduce resistance

Compressive zone to reduce dicing defects

Passive methods of loose die identification

Contacts having a geometry to reduce resistance

Step pyramid shaped structure to reduce dicing defects

Low resistance contact for transistors

Enhancement of iso-via reliability

Photodiode structures

Semiconductor via structure with lower electrical resistance

Photodiode structures

Managed integrated circuit power supply distribution

Low resistance contact for transistors

Optimizing error correcting code in three-dimensional stacked memory

Three-dimensional stacked memory access optimization

Three-dimensional stacked memory optimizations for latency and power

Managed integrated circuit power supply distribution

Shielding structures between optical waveguides

Photodiode structures

PROTECTIVE LINER BETWEEN A GATE DIELECTRIC AND A GATE CONTACT

Metalization repair in semiconductor wafers

Testing mechanism for a proximity fail probability of defects across integrated chips

Lateral non-volatile storage cell

Lateral non-volatile storage cell

Photodiode structures

Contacts having a geometry to reduce resistance

Photodiode structures

Method and structures for personalizing lithography

Structure and method for fully depleted silicon on insulator structure for threshold voltage modification

Method of optimizing wire RC for device performance and reliability

Metalization repair in semiconductor wafers

METALIZATION REPAIR IN SEMICONDUCTOR WAFERS

Independently driving built-in self test circuitry over a range of operating conditions

Photodiode structures

Protective liner between a gate dielectric and a gate contact

Semiconductor via structure with lower electrical resistance

Semiconductor power and performance optimization

Enhancement of iso-via reliability

Testing mechanism for a proximity fail probability of defects across integrated chips

Contacts having a geometry to reduce resistance

Dynamic noise mitigation in integrated circuit devices using local clock buffers

Semiconductor via structure with lower electrical resistance

Photodiode structures

Photodiode structures

Waveguide switch with tuned photonic microring

Method of optimizing wire RC for device performance and reliability

Deterministic current based frequency optimization of processor chip

Deterministic current based frequency optimization of processor chip

Optimized wires for resistance or electromigration

Optimized wires for resistance or electromigration

Power gating and clock gating in wiring levels

Immunity to inline charging damage in circuit designs

Immunity to inline charging damage in circuit designs

Bias-temperature induced damage mitigation circuit

Bias-temperature induced damage mitigation circuit

Immunity to inline charging damage in circuit designs

Optimized wires for resistance or electromigration

Photodiode structures

Reducing the impact of charged particle beams in critical dimension analysis

Enhancement of iso-via reliability

Signal monitoring of through-wafer vias using a multi-layer inductor

ENHANCEMENT OF ISO-VIA RELIABILITY

Circuit design for balanced logic stress

Circuit design for balanced logic stress

Method of self-correcting power grid for semiconductor structures

Stress balancing of circuits

Shielding structures between optical waveguides

Signal monitoring of through-wafer vias using a multi-layer inductor

Thermal energy dissipation using backside thermoelectric devices

Self-correcting power grid for semiconductor structures method

Encapsulated sensors

Semiconductor device burn-in stress method and system

NANOPARTICLES FOR MAKING SUPERCAPACITOR AND DIODE STRUCTURES

Determining chip burn-in workload using emulated application condition

Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)

Methods for testing integrated circuits of wafer and testing structures for integrated circuits

Vertically curved waveguide

Vertical bend waveguide coupler for photonics applications

On chip electrostatic discharge (ESD) event monitoring

Semiconductor-on-oxide structure and method of forming

Light activated test connections

Methodology of grading reliability and performance of chips across wafer

Semiconductor-on-insulator (SOI) deep trench capacitor

Creating deep trenches on underlying substrate

Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)

Semiconductor-on-oxide structure and method of forming

Creating deep trenches on underlying substrate

Semiconductor structures using replacement gate and methods of manufacture

Micro-electro-mechanical system tiltable lens

USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES

3-dimensional integrated circuit testing using MEMS switches with tungsten cone contacts

Use of contacts to create differential stresses on devices

Micromirrors for color electronic paper and design structures for same

Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method

Fuse for three dimensional solid-state battery

Passive resonator, a system incorporating the passive resonator for real-time intra-process monitoring and control and an associated method