Brian A. Winstead

Split gate nanocrystal memory integration

Split-gate non-volatile memory cells having gap protection zones

Split gate non-volatile memory cell

METHODS AND STRUCTURES FOR SPLIT GATE MEMORY

SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER

Programming a split gate bit cell

Method of making a non-volatile memory (NVM) cell structure

Semiconductor device including an active region and two layers having different stress characteristics

Method for preconditioning thin film storage array for data retention

Split gate memory device with gap spacer

Methods and systems for erase biasing of split-gate non-volatile memory cells

Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor

Transistors with different threshold voltages

SPLIT GATE MEMORY DEVICE WITH GAP SPACER

Memory with discrete storage elements

Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner

Method of making a semiconductor structure useful in making a split gate non-volatile memory cell

Split-gate non-volatile memory cells having improved overlap tolerance

Split-gate non-volatile memory cell having improved overlap tolerance and method therefor

Method for forming a split gate device

Method of forming a semiconductor device featuring a gate stressor and semiconductor device

Method of making a semiconductor structure useful in making a split gate non-volatile memory cell

Split gate non-volatile memory cell with improved endurance and method therefor

Method for making a stressed non-volatile memory device

Stressed semiconductor device and method for making

Nonvolatile split gate memory cell having oxide growth

Split-gate non-volatile memory cell and method

Method for forming one transistor DRAM cell structure

Memory having P-type split gate memory cells and method of operation

Method of forming a split gate memory device and apparatus

Split gate non-volatile memory cell with improved endurance and method therefor

Source/drain stressors formed using in-situ epitaxial growth

Method of forming a semiconductor device featuring a gate stressor and semiconductor device

Electronic device including a transistor structure having an active region adjacent to a stressor layer

Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner

Source/drain stressor and method therefor

Split-gate thin film storage NVM cell with reduced load-up/trap-up effects

Semiconductor device including an active region and two layers having different stress characteristics

Electronic device including a heterojunction region

One transistor DRAM cell structure

Transistor with asymmetry for data storage circuitry

Dual surface SOI by lateral epitaxial overgrowth

Engineering strain in thick strained-SOI substrates

Semiconductor device with stressors and method therefor

Electronic device including a static-random-access memory cell and a process of forming the electronic device

Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device

Semiconductor structure with reduced gate doping and methods for forming thereof

Method and apparatus for performance enhancement in an asymmetrical semiconductor device