Apex, North Carolina
United States
46
2015-02-24
The entities that hold a legal rights for patent applications filed by inventor Marchand Patrick R.:
Patrick R. Marchand from Apex, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Isochronous hub contracts
#2 | 2014-10-28Padding buffer requests to avoid reads of invalid data
#3 | 2014-10-21Multi-class data cache policies
#4 | 2014-10-14Compression status caching
#5 | 2014-08-21Methods and apparatus for scalable array processor interrupt detection and response
#6 | 2014-08-21Compression status bit cache and backing store
#7 | 2014-03-13Methods and apparatus for adapting pipeline stage latency based on instruction type
#8 | 2014-02-27System core for transferring data between an external device and memory
#9 | 2013-11-26Compression status bit cache with deterministic isochronous latency
#10 | 2013-10-24Methods and apparatus for scalable array processor interrupt detection and response
#11 | 2013-08-06Storing dynamically sized buffers within a cache
#12 | 2013-06-11Cache and associated method with frame buffer managed dirty data pull and high-priority clean mechanism
#13 | 2013-05-16Techniques for evicting dirty data from a cache using a notification sorter and count thresholds
#14 | 2013-01-03System core for transferring data between an external device and memory
#15 | 2012-09-18Method and system for converting data formats using a shared cache coupled between clients and an external memory
#16 | 2012-08-14System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy
#17 | 2012-07-31Using a data cache array as a DRAM load/store buffer
#18 | 2012-07-05Methods and apparatus for scalable array processor interrupt detection and response
#19 | 2012-05-17System core for transferring data between an external device and memory
#20 | 2012-04-10L2 ECC implementation
#21 | 2012-03-13Cache-based control of atomic operations in conjunction with an external ALU block
#22 | 2012-03-06Configurable cache occupancy policy
#23 | 2012-01-31Cache-based control of atomic operations in conjunction with an external ALU block
#24 | 2012-01-17L2 ECC implementation
#25 | 2011-11-15System, method and frame buffer logic for evicting dirty data from a cache using counters and data types
#26 | 2011-09-08System core for transferring data between an external device and memory
#27 | 2011-06-14Method and system for reordering isochronous hub streams
#28 | 2011-04-14Efficient line and page organization for compression status bit caching
#29 | 2011-03-24Methods and apparatus for scalable array processor interrupt detection and response
#30 | 2011-03-24Virtual channels for effective packet transfer
#31 | 2010-12-16Methods and apparatus for adapting pipeline stage latency based on instruction type
#32 | 2010-10-05Methods and apparatus for adapting pipeline stage latency based on instruction type
#33 | 2010-06-17Deadlock avoidance by marking CPU traffic as special
#34 | 2010-06-03Compression status bit cache and backing store
#35 | 2009-07-21Out of order graphics L2 cache
#36 | 2009-03-05System core for transferring data between an external device and memory
#37 | 2008-09-11Methods and apparatus for scalable array processor interrupt detection and response
#38 | 2008-05-22Methods and apparatus for power control in a scalable array of processor elements
#39 | 2008-03-04Providing parallel operand functions using register file and extra path storage
#40 | 2007-09-04System core for transferring data between an external device and memory
#41 | 2005-11-15Methods and apparatus for power control in a scalable array of processor elements
#42 | 2005-10-06Methods and apparatus for power control in a scalable array of processor elements
#43 | 2005-06-09Cascaded event detection modules for generating combined events interrupt for processor action
#44 | 2005-02-03Methods and apparatus for scalable array processor interrupt detection and response
#45 | 2005-01-18Methods and apparatus for power control in a scalable array of processor elements
#46 | 2005-01-11Methods and apparatus for scalable array processor interrupt detection and response
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