Milpitas, California
United States
44
2024-08-15
The entities that hold a legal rights for patent applications filed by inventor Chen Jie:
Jie Chen from Milpitas, US has applied for patents for these inventions. The list has both pending applications and granted patents:
VALID DATA RETRIEVAL FOR GARBAGE COLLECTION
#2 | 2024-07-18CONCATENATED ERROR CORRECTING CODES
#3 | 2024-03-14Valid data retrieval for garbage collection
#4 | 2023-11-09SELECTING READ REFERENCE VOLTAGE USING HISTORICAL DECODING INFORMATION
#5 | 2023-10-26Systems and methods for an ECC architecture with memory mapping
#6 | 2023-10-26Systems and methods for an ECC architecture with memory mapping
#7 | 2023-06-29Concatenated error correcting codes
#8 | 2023-04-06Systems and methods for decoding codewords in a same page with historical decoding information
#9 | 2023-03-30Selecting read reference voltage using historical decoding information
#10 | 2023-03-23Error recovery using adaptive LLR lookup table
#11 | 2023-03-16Non-volatile storage controller with partial logical-to-physical (L2P) address translation table
#12 | 2023-03-16Reference voltage adjustment based on post-decoding and pre-decoding state information
#13 | 2023-01-31Systems and methods for decoding codewords in a same page with historical decoding information
#14 | 2023-01-05Robustness-aware NAND flash management
#15 | 2022-12-01Concatenated error correcting codes
#16 | 2022-11-10Non-volatile storage controller with partial logical-to-physical (L2P) address translation table
#17 | 2022-11-10Partial logical-to-physical (L2P) address translation table for multiple namespaces
#18 | 2022-09-22Error recovery using adaptive LLR lookup table
#19 | 2022-07-14Grouping flash storage blocks based on robustness for cache program operations and regular program operations
#20 | 2022-07-07Reference voltage adjustment based on post-decoding and pre-decoding state information
#21 | 2022-06-09Cache program with backup blocks
#22 | 2022-04-21Electrical mirroring by NAND flash controller
#23 | 2022-04-14Systems and methods for an ECC architecture with memory mapping
#24 | 2022-04-14Systems and methods for an ECC architecture with memory mapping
#25 | 2022-03-24Temperature assisted NAND flash management
#26 | 2022-02-17Command based on-die termination for high-speed NAND interface
#27 | 2022-01-20Systems and methods for decoding error correcting codes with historical decoding information
#28 | 2021-12-09Electrical mirroring by NAND flash controller
#29 | 2021-10-21Command based on-die termination for high-speed NAND interface
#30 | 2021-10-07Systems and methods for decoding error correcting codes with historical decoding information
#31 | 2021-01-07Systems and methods for ultra fast ECC with parity
#32 | 2020-10-01Systems and methods for an ECC architecture with prioritized task queues
#33 | 2020-09-17Systems and methods for an ECC architecture with memory mapping
#34 | 2020-04-23SYSTEMS AND METHODS FOR A HYBRID NON-VOLATILE STORAGE SYSTEM
#35 | 2020-02-20Systems and methods for decoding error correcting codes
#36 | 2020-01-30Systems and methods for decoding error correcting codes with self-generated LLR
#37 | 2019-12-19Systems and methods for ultra fast ECC with parity
#38 | 2019-11-07Data storage device with selective connection to non-volatile memories
#39 | 2019-05-16Systems and methods for decoding error correcting codes
#40 | 2019-05-16Systems and methods for decoding error correcting codes
#41 | 2019-04-25Systems and methods for fast access of non-volatile storage devices
#42 | 2019-04-04Systems and methods for decoding error correcting codes
#43 | 2017-09-05Methods and systems for parallelizing high throughput iterative decoders
#44 | 2017-02-16FLEXIBLE INTERFACE FOR NAND FLASH MEMORY
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