Inventor profile of:

William Michael LYE

City:

Coquitlam

Country:

Canada

Published Applications:

20

Last publication date:

2019-01-31

Top Assignees for applications by William Michael LYE

The entities that hold a legal rights for patent applications filed by inventor LYE William Michael:

Recent patent applications by LYE William Michael

William Michael LYE from Coquitlam, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-01-31
US20190036539A1
Electricity

Radio frequency flash ADC circuits

#2 | 2018-03-29
US20180091166A1
Electricity

Radio frequency flash ADC circuits

#3 | 2017-05-11
US20170134037A1
Electricity

Digital-to-analog converter system and method

#4 | 2017-02-23
US20170054448A1
Electricity

Radio frequency flash ADC circuits

#5 | 2016-08-09
US14676142
Electricity

Digital to-analog converter system and method

#6 | 2016-01-05
US14791321
Electricity

Low-noise flexible frequency clock generation from two fixed-frequency references

#7 | 2015-12-29
US14791329
Electricity

Low-noise flexible frequency clock generation from two fixed-frequency references

#8 | 2015-12-29
US13910016
Electricity

System and method for synchronizing local oscillators

#9 | 2015-12-15
US14791319
Electricity

Low-noise flexible frequency clock generation from two fixed-frequency references

#10 | 2015-09-01
US14580099
Electricity

Scrambler with built in test capabilities for unary DAC

#11 | 2015-08-18
US14295742
Electricity

Low-noise flexible frequency clock generation from two fixed-frequency references

#12 | 2015-07-28
US14604024
Electricity

Quantization noise-shaping device

#13 | 2014-07-08
US13624719
-

Interleaved digital to analog conversion

#14 | 2013-06-18
US12627667
-

DSP-based diagnostics for monitoring a SerDes link

#15 | 2011-07-26
US12610074
-

Jitter attenuation with a fractional-N clock synthesizer

#16 | 2007-12-13
US20070285120A1
Electricity

Configurable voltage mode transmitted architecture with common-mode adjustment and novel pre-emphasis

#17 | 2007-10-30
US11691859
-

Systems and methods for actively-peaked current-mode logic

#18 | 2007-04-17
US11177853
-

Systems and methods for translation of signal levels across voltage domains

#19 | 2007-04-10
US10820381
-

Systems and methods for actively-peaked current-mode logic

#20 | 2006-04-04
US10384585
-

Joint equalization and timing acquisition for RZ signals

InventorID:

1807026 ⎘