Charles Jay Alpert

Creating regional routing blockages in integrated circuit design

Physical synthesis optimization with fast metric check

DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUST CLOCK NETWORK DESIGN

Direct current circuit analysis based clock network design

Early design cycle optimization

Solving traffic congestion using vehicle grouping

Solving traffic congestion using vehicle grouping

Latch clustering with proximity to local clock buffers

Solving traffic congestion using vehicle grouping

Solving network traffic congestion using device grouping

Designing a robust power efficient clock distribution network

Early design cycle optimzation

Solving congestion using net grouping

Congestion aware routing using random points

COST-EFFECTIVE AND RELIABLE UTILITIES DISTRIBUTION NETWORK

Multi-patterning lithography aware cell placement in integrated circuit design

WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN

Timing driven routing in integrated circuit design

Routing and timing using layer ranges

Latch clustering with proximity to local clock buffers

Multiple threshold voltage cell families based integrated circuit design

Object placement in integrated circuit design

Method of and system for buffer insertion, layer assignment, and wire sizing using wire codes

Practical methodology for early buffer and wire resource allocation

Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model