Gi-Joon Nam

Fault-tolerant power-driven synthesis

Error checking and correction for NAND flash devices

Fault-tolerant power-driven synthesis

Power driven synaptic network synthesis

Power-driven synthesis under latency constraints

Simultaneous multi-page commands for non-volatile memories

Multi-Level Cell Flash Memory Control Mechanisms

Virtual sub-net based routing

Virtual sub-net based routing

Error checking and correction for NAND flash devices

Apportioning synthesis effort for better timing closure

Creating regional routing blockages in integrated circuit design

Routing centric design closure

Structured placement of latches/flip-flops to minimize clock power in high-performance designs

Latch clustering with proximity to local clock buffers

Scheduling for parallel processing of regionally-constrained placement problem

Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design

Post-placement cell shifting

Timing refinement re-routing

Element placement in circuit design based on preferred location

Local objective optimization in global placement of an integrated circuit design

Multi-patterning lithography aware cell placement in integrated circuit design

Accuracy pin-slew mode for gate delay calculation

WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN

Scheduling for parallel processing of regionally-constrained placement problem

Clock optimization with local clock buffer control optimization

Latch clustering with proximity to local clock buffers

Electronic design automation object placement with partially region-constrained objects

Detailed routability by cell placement

Post-placement cell shifting

Object placement in integrated circuit design

Incremental timing optimization and placement

Scheduling for parallel processing of regionally-constrained placement problem

Legalization of VLSI circuit placement with blockages using hierarchical row slicing

Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors

Clock aware placement

Constrained detailed placement

METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS

Clustering techniques for faster and better placement of VLSI circuits

Clustering-based multilevel quadratic placement

Stability metrics for placement to quantify the stability of placement algorithms

Hybrid quadratic placement with multiple linear system solvers

Latch placement technique for reduced clock signal skew