Beacon, New York
United States
52
2020-11-19
The entities that hold a legal rights for patent applications filed by inventor Kumar Arvind:
Arvind Kumar from Beacon, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Asymmetric high-k dielectric for reducing gate induced drain leakage
#2 | 2020-01-23SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
#3 | 2019-12-19THICK GATE OXIDE FET INTEGRATED WITH FDSOI WITHOUT ADDITIONAL THICK OXIDE FORMATION
#4 | 2019-09-26Asymmetric high-k dielectric for reducing gate induced drain leakage
#5 | 2019-06-13SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
#6 | 2018-09-27Semiconductor structure with integrated passive structures
#7 | 2018-03-15Asymmetric high-k dielectric for reducing gate induced drain leakage
#8 | 2018-03-01Asymmetric high-k dielectric for reducing gate induced drain leakage
#9 | 2018-03-01Asymmetric high-k dielectric for reducing gate induced drain leakage
#10 | 2017-11-23Semiconductor structure with integrated passive structures
#11 | 2017-10-05Method and IC structure for increasing pitch between gates
#12 | 2017-08-17Semiconductor structure with integrated passive structures
#13 | 2017-07-13Methods and control systems of resistance adjustment of resistors
#14 | 2017-06-22Junction butting structure using nonuniform trench shape
#15 | 2017-06-22Asymmetric high-k dielectric for reducing gate induced drain leakage
#16 | 2017-06-15THICK GATE OXIDE FET INTEGRATED WITH FDSOI WITHOUT ADDITIONAL THICK OXIDE FORMATION
#17 | 2017-05-04Asymmetric high-k dielectric for reducing gate induced drain leakage
#18 | 2017-03-16Asymmetric semiconductor device and method of forming same
#19 | 2016-11-10FinFET with constrained source-drain epitaxial region
#20 | 2016-10-20Semiconductor structure with integrated passive structures
#21 | 2016-10-20Semiconductor structure with integrated passive structures
#22 | 2016-09-15Asymmetric high-K dielectric for reducing gate induced drain leakage
#23 | 2016-09-08Asymmetric high-k dielectric for reducing gate induced drain leakage
#24 | 2016-09-08Asymmetric high-K dielectric for reducing gate induced drain leakage
#25 | 2016-07-26Methods and control systems of resistance adjustment of resistors
#26 | 2016-07-14Asymmetric high-K dielectric for reducing gate induced drain leakage
#27 | 2016-07-14Asymmetric high-k dielectric for reducing gate induced drain leakage
#28 | 2016-07-14Asymmetric high-k dielectric for reducing gate induced drain leakage
#29 | 2016-07-14Asymmetric high-K dielectric for reducing gate induced drain leakage
#30 | 2016-07-14Asymmetric high-k dielectric for reducing gate induced drain leakage
#31 | 2016-06-16CMOS gate contact resistance reduction
#32 | 2016-02-11FinFET with constrained source-drain epitaxial region
#33 | 2016-01-14FinFET with constrained source-drain epitaxial region
#34 | 2016-01-14Semiconductor structure with integrated passive structures
#35 | 2016-01-14Semiconductor structure with integrated passive structures
#36 | 2015-12-31Junction butting structure using nonuniform trench shape
#37 | 2015-12-24Buried signal transmission line
#38 | 2015-12-10Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device
#39 | 2015-10-01Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device
#40 | 2015-05-07NON-VOLATILE MEMORY DEVICE INTEGRATED WITH CMOS SOI FET ON A SINGLE CHIP
#41 | 2015-03-26Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors
#42 | 2014-10-23Non-volatile memory device integrated with CMOS SOI FET on a single chip
#43 | 2014-09-11Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication
#44 | 2014-07-24Method of forming a gated diode structure for eliminating RIE damage from cap removal
#45 | 2014-07-10Fin-shaped field effect transistor (finFET) structures having multiple threshold voltages (Vt) and method of forming
#46 | 2014-05-01Method and structure for body contacted FET with reduced body resistance and source to drain contact leakage
#47 | 2014-04-17ION IMPLANTATION TUNING TO ACHIEVE SIMULTANEOUS MULTIPLE IMPLANT ENERGIES
#48 | 2014-03-27Semiconductor structure with integrated passive structures
#49 | 2013-12-12Gated diode structure for eliminating RIE damage from cap removal
#50 | 2013-04-11ELECTRICAL MASK INSPECTION
#51 | 2009-12-10SOI transistor having a carrier recombination structure in a body
#52 | 2009-05-14Field effect transistor containing a wide band gap semiconductor material in a drain
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