Perry H. Pelley

Memory circuit having concurrent writes and method therefor

Memory circuit having increased write margin and method therefor

Memory circuit and method for increased write margin

Small signal input buffer

Memory repair system and method therefor

Direct interface between SRAM and non-volatile memory providing space efficiency by matching pitch in both memories

Partitioned memory having pipeline writes

Memory with read circuitry and method of operating

Mismatch-compensated sense amplifier for highly scaled technology

Non-volatile static random access memory (NVSRAM) having a shared port

Die stack address bus having a programmable width

Non-volatile memory using bi-directional resistive elements and capacitive elements

Non-volatile memory using bi-directional resistive elements

Methods and structures for multiport memory devices

Non-volatile memory using bi-directional resistive elements

Memory with redundancy

Defective die replacement in a die stack

Method and apparatus for beam control with optical MEMS beam waveguide

Temperature threshold circuit with hysteresis

Memory redundancy to replace addresses with multiple errors

Voltage generator with ramp rate control

Microelectronic assembly having a heat spreader for a plurality of die

Thin low profile strip dual in-line memory module

Capacitively coupled input buffer

Memory ECC with hard and soft error detection and management

Wirebond recess for stacked die

Stacked semiconductor devices

Edge coupling of semiconductor dies

Level shifter with static precharge circuit

Charge pump system and method of operation

Optical wafer and die probe testing

Die stack with optical TSVs

Optical die test interface with separate voltages for adjacent electrodes

Optical redundancy

Optical backplane mirror

Integration of a MEMS beam with optical waveguide and deflection in two dimensions

Communication system die stack

Four port memory with multiple cores

Self adjusting reference for input buffer

Synchronous multiple port memory with asynchronous ports

Multiport memory with matching address control

Gate security feature

Synchronous multiple port memory with asynchronous ports

Systems and methods for reduced coupling between digital signal lines

Multiport memory with matching address control

Multiport memory with matching address and data line control

Bus signal encoded with data and clock signals

Transmission system

Microelectronic assembly having a heat spreader for a plurality of die

Techniques for reducing inductance in through-die vias of an electronic assembly

SRAM bit cell with reduced bit line pre-charge voltage

Word line driver circuits and methods for SRAM bit cell with reduced bit line pre-charge voltage

Methods and structures for multiport memory devices

Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

Multi-port register file with multiplexed data

Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

Bipolar primary sense amplifier

Semiconductor devices with nonconductive vias

Stacked semiconductor devices

Stacked semiconductor die with continuous conductive vias

ROM memory device

Static random access memory (SRAM) having bit cells accessible by separate read and write paths

System having multiple voltage tiers and method therefor

System and method for communicating between multiple voltage tiers

Edge mounted integrated circuits with heat sink

Voltage boosting system with slew rate control and method thereof

Method and circuit for charging and discharging a circuit node

Driver with selectable output impedance

Optical communication integration

Free-space optical communication system

High bandwidth cache-to-processing unit communication in a multiple processor/cache system

Power supply selection for multiple circuits on an integrated circuit

System and method for testing and providing an integrated circuit having multiple modules or submodules

MEMORY SYSTEM HAVING GLOBAL BUFFERED CONTROL FOR MEMORY MODULES

Embedded substrate interconnect for underside contact to source and drain regions

Memory with increased write margin bitcells

Memory having sense time of variable duration

Memory with level shifting word line driver and method thereof

Memory with clocked sense amplifier

Embedded substrate interconnect for underside contact to source and drain regions

Method and apparatus for low voltage write in a static random access memory

Integrated circuit with programmable-impedance output buffer and method therefor

Memory having variable refresh control and method therefor

Automatic hidden refresh in a dram and method therefor

Memory with serial input/output terminals for address and data and method therefor

Cache line memory and method therefor

Inductive device including bond wires