Inventor profile of:

Gary L. Miller

City:

Austin, Texas

Country:

United States

Published Applications:

22

Last publication date:

2024-08-15

Top Assignees for applications by Gary L. Miller

The entities that hold a legal rights for patent applications filed by inventor Miller Gary L.:

Recent patent applications by Miller Gary L.

Gary L. Miller from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-08-15
US20240272978A1
Physics

SYSTEMS AND METHODS FOR DEBUGGING MULTI-CORE PROCESSORS WITH CONFIGURABLE ISOLATED PARTITIONS

#2 | 2019-12-05
US20190370212A1
Physics

Inter-processor communication method for access latency between system-in-package (SIP) dies

#3 | 2019-12-05
US20190370211A1
Physics

Inter-processor communication and signaling system and method

#4 | 2017-09-12
US15478000
Electricity

Systems and methods for supplying reference voltage to multiple die of different technologies in a package

#5 | 2016-10-11
US14788363
Physics

Synchronous communication between system in package (SiP) devices

#6 | 2016-06-21
US14719549
Physics

Clock signal alignment for system-in-package (SIP) devices

#7 | 2015-06-25
US20150179286A1
Physics

System in a package (SiP)

#8 | 2015-02-19
US20150052405A1
Physics

Data bus network interface module and method therefor

#9 | 2014-08-28
US20140244878A1
Physics

Methods and systems for address mapping between host and expansion devices within system-in-package (SiP) solutions

#10 | 2014-08-28
US20140244873A1
Physics

Methods and systems for interconnecting host and expansion devices within system-in-package (SiP) solutions

#11 | 2014-03-06
US20140068345A1
Physics

Method and apparatus for filtering trace information

#12 | 2014-03-06
US20140068344A1
Physics

Method and apparatus for filtering trace information

#13 | 2013-04-18
US20130097462A1
Physics

EMBEDDED LOGIC ANALYZER

#14 | 2013-04-04
US20130086283A1
Physics

Interface system and method with backward compatibility

#15 | 2013-03-28
US20130080748A1
Physics

Multi-processor data processing system having synchronized exit from debug mode and method therefor

#16 | 2013-01-03
US20130007533A1
Physics

DATA PROCESSING SYSTEM HAVING A SEQUENCE PROCESSING UNIT AND METHOD OF OPERATION

#17 | 2013-01-03
US20130007532A1
Physics

Data processing system having a sequence processing unit and method of operation

#18 | 2012-02-09
US20120036400A1
Physics

Data processing system with peripheral configuration information error detection

#19 | 2011-03-31
US20110078521A1
Physics

Transition fault testing for a non-volatile memory

#20 | 2010-05-13
US20100122001A1
Electricity

Technique for interconnecting integrated circuits

#21 | 2010-05-13
US20100117242A1
Electricity

TECHNIQUE FOR PACKAGING MULTIPLE INTEGRATED CIRCUITS

#22 | 2008-12-04
US20080301511A1
Physics

Integrated circuit with continuous testing of repetitive functional blocks

InventorID:

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