Inventor profile of:

Robert E. Galbraith

City:

Rochester, Minnesota

Country:

United States

Published Applications:

32

Last publication date:

2020-12-03

Top Assignees for applications by Robert E. Galbraith

The entities that hold a legal rights for patent applications filed by inventor Galbraith Robert E.:

Recent patent applications by Galbraith Robert E.

Robert E. Galbraith from Rochester, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-12-03
US20200379915A1
Physics

Persistent logical to virtual table

#2 | 2020-07-23
US20200233475A1
Physics

Thread checkpoint table for computer processor

#3 | 2019-04-18
US20190114217A1
Physics

Corrupt logical block addressing recovery scheme

#4 | 2018-03-29
US20180089097A1
Physics

Implementing hardware accelerator for storage write cache management for managing cache destage rates and thresholds for storage write cache

#5 | 2017-05-11
US20170132155A1
Physics

Implementing hardware accelerator for storage write cache management

#6 | 2017-05-11
US20170132154A1
Physics

Implementing hardware accelerator for storage write cache management for managing cache destage rates and thresholds for storage write cache

#7 | 2017-05-11
US20170132153A1
Physics

Implementing hardware accelerator for storage write cache management for managing cache line updates for writes, reads, and destages in storage write cache

#8 | 2017-05-11
US20170132152A1
Physics

Implementing hardware accelerator for storage write cache management for identification of data age in storage write cache

#9 | 2017-05-11
US20170132151A1
Physics

Implementing hardware accelerator for storage write cache management for destage operations from storage write cache

#10 | 2017-05-11
US20170132146A1
Physics

Implementing hardware accelerator for storage write cache management for simultaneous read and destage operations from storage write cache

#11 | 2017-05-11
US20170132145A1
Physics

Implementing hardware accelerator for storage write cache management for reads with partial read hits from storage write cache

#12 | 2017-05-11
US20170132143A1
Physics

Implementing hardware accelerator for storage write cache management for merging data with existing data on fast writes to storage write cache

#13 | 2017-05-11
US20170132142A1
Physics

Implementing hardware accelerator for storage write cache management for writes to storage write cache

#14 | 2017-05-11
US20170132138A1
Physics

Implementing hardware accelerator for storage write cache management for managing cache line updates for purges from storage write cache

#15 | 2017-05-11
US20170132137A1
Physics

Implementing hardware accelerator for storage write cache management for reads from storage write cache

#16 | 2017-05-11
US20170131909A1
Physics

Implementing hardware accelerator for storage write cache management with cache line manipulation

#17 | 2015-02-19
US20150052385A1
Physics

Implementing enhanced data caching and takeover of non-owned storage devices in dual storage device controller configuration with data in write cache

#18 | 2014-04-10
US20140101479A1
Physics

Implementing storage adapter performance control

#19 | 2014-04-10
US20140101455A1
Physics

Implementing dynamic banding of self encrypting drive

#20 | 2013-12-19
US20130339784A1
Physics

ERROR RECOVERY IN REDUNDANT STORAGE SYSTEMS

#21 | 2013-08-22
US20130219119A1
Physics

Writing new data of a first block size to a second block size using a write-write mode

#22 | 2013-01-03
US20130007545A1
Physics

Managing logically bad blocks in storage devices

#23 | 2012-12-06
US20120311222A1
Physics

Implementing device physical location identification in serial attached SCSI (SAS) fabric using resource path groups

#24 | 2012-11-29
US20120304198A1
Physics

Implementing storage adapter performance optimization with chained hardware operations minimizing hardware/firmware interactions

#25 | 2012-11-29
US20120304001A1
Physics

Implementing storage adapter performance optimization with chained hardware operations and error recovery firmware path

#26 | 2012-11-29
US20120303909A1
Physics

Implementing storage adapter performance optimization with enhanced hardware and software interface

#27 | 2012-11-29
US20120303886A1
Physics

Implementing storage adapter performance optimization with hardware chains to select performance path

#28 | 2012-11-29
US20120303859A1
Physics

Implementing storage adapter performance optimization with parity update footprint mirroring

#29 | 2012-11-22
US20120297272A1
Physics

Implementing enhanced IO data conversion with protection information model including parity format of data integrity fields

#30 | 2012-11-01
US20120278528A1
Physics

IIMPLEMENTING STORAGE ADAPTER WITH ENHANCED FLASH BACKED DRAM MANAGEMENT

#31 | 2010-10-14
US20100262868A1
Physics

Managing possibly logically bad blocks in storage devices

#32 | 2010-08-05
US20100199039A1
Physics

Systems and Methods for Optimizing Host Reads and Cache Destages in a Raid System

InventorID:

18484 ⎘