Warwick, New York
United States
18
2020-06-18
The entities that hold a legal rights for patent applications filed by inventor Strane Jay W.:
Jay W. Strane from Warwick, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Dual width finned semiconductor structure
#2 | 2020-06-04Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal
#3 | 2020-05-14Semiconductor fins with dielectric isolation at fin bottom
#4 | 2020-01-23Controlling active fin height of FinFET device
#5 | 2019-12-19Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal
#6 | 2019-12-05Dual width finned semiconductor structure
#7 | 2019-10-10Semiconductor fins with dielectric isolation at fin bottom
#8 | 2019-02-28Protection of low temperature isolation fill
#9 | 2019-02-28Protection of low temperature isolation fill
#10 | 2017-08-17Uniform dielectric recess depth during fin reveal
#11 | 2017-08-17Uniform dielectric recess depth during fin reveal
#12 | 2017-05-04Uniform dielectric recess depth during fin reveal
#13 | 2017-05-04Uniform dielectric recess depth during fin reveal
#14 | 2012-08-16Semiconductor structures having improved contact resistance
#15 | 2012-05-31Semiconductor structures having improved contact resistance
#16 | 2011-12-08Replacement gate MOSFET with self-aligned diffusion contact
#17 | 2010-01-14Methods for forming high performance gates and structures thereof
#18 | 2007-10-25IMPROVED THERMAL BUDGET USING NICKEL BASED SILICIDES FOR ENHANCED SEMICONDUCTOR DEVICE PERFORMANCE
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