Ralf RICHTER

SEMICONDUCTOR DEVICE INCLUDING GATE WITH DIFFERENT LATERALLY ADJACENT SECTIONS AND METHOD

STRUCTURE WITH BURIED DOPED REGION FOR COUPLING SOURCE LINE CONTACT TO GATE STRUCTURE OF MEMORY CELL

Non-volatile memory structure using semiconductor layer as floating gate and bulk semiconductor substrate as channel region

Semiconductor device with a memory device and a high-K metal gate transistor

Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure

Efficient main spacer pull back process for advanced VLSI CMOS technologies

Epitaxial growth of silicon for FinFETS with non-rectangular cross-sections

Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby

Methods of removing gate cap layers in CMOS applications

Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode

Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials

Processes for forming integrated circuits and integrated circuits formed thereby

METHODS FOR DEPOSITION OF TUNGSTEN IN THE FABRICATION OF AN INTEGRATED CIRCUIT

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

Method of making capacitor with a sealing liner and semiconductor device comprising same

Semiconductor fuses in a semiconductor device comprising metal gates

TECHNIQUE FOR REDUCING TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS

Enhancing transistor performance by reducing exposure to oxygen plasma in a dual stress liner approach

Method of forming metal gates and metal contacts in a common fill process

ULTRAVIOLET (UV)-REFLECTING FILM FOR BEOL PROCESSING

Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials

Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process

Methods for fabricating semiconductor devices having local contacts

Hybrid contact structure with low aspect ratio contacts in a semiconductor device

Enhancement of ultraviolet curing of tensile stress liner using reflective materials

Semiconductor devices having through-contacts and related fabrication methods

Increasing robustness of a dual stress liner approach in a semiconductor device by applying a wet chemistry

Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric

Replacement Gate Approach for High-K Metal Gate Stacks Based on a Non-Conformal Interlayer Dielectric

Selective shrinkage of contact elements in a semiconductor device

Replacement gate approach for high-k metal gate stacks by avoiding a polishing process for exposing the placeholder material

Semiconductor device comprising metal gate structures formed by a replacement gate approach and efuses including a silicide

Technique for enhancing transistor performance by transistor specific contact design

Method of reducing contamination by providing a removable polymer protection film during microstructure processing

Method for forming a metal silicide having a lower potential for containing material defects

Semiconductor resistors formed at a lower height level in a semiconductor device comprising metal gates

Cap removal in a high-k metal gate electrode structure by using a sacrificial fill material

Method for forming semiconductor fuses in a semiconductor device comprising metal gates

Forming semiconductor resistors in a semiconductor device comprising metal gates by increasing etch resistivity of the resistors

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

Method of manufacturing a CMOS device including molecular storage elements in a via level

Using high-k dielectrics as highly selective etch stop materials in semiconductor devices

Cap layer removal in a high-K metal gate stack by using an etch process

Contact optimization for enhancing stress transfer in closely spaced transistors

Non-insulating stressed material layers in a contact level of semiconductor devices

Technique for compensating for a difference in deposition behavior in an interlayer dielectric material

Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material

Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors

Reduced topography-related irregularities during the patterning of two different stress-inducing layers in the contact level of a semiconductor device

REDUCING LEAKAGE AND DIELECTRIC BREAKDOWN IN DIELECTRIC MATERIALS OF METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY FORMING RECESSES

Semiconductor device comprising a carbon-based material for through hole vias

Cold temperature control in a semiconductor device

Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors

Method for forming a substrate contact for advanced SOI devices based on a deep trench capacitor configuration

SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME

Method of forming an interlayer dielectric material having different removal rates during CMP

Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material

Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials

Stressed interlayer dielectric with reduced probability for void generation in a semiconductor device by using an intermediate etch control layer of increased thickness

Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process

Stress transfer by sequentially providing a highly stressed etch stop material and an interlayer dielectric in a contact layer stack of a semiconductor device

Technique for compensating for a difference in deposition behavior in an interlayer dielectric material

SIDEWALL PROTECTION LAYER

Increased reliability for a contact structure to connect an active region with a polysilicon line

Semiconductor device including field effect transistors laterally enclosed by interlayer dielectric material having increased intrinsic stress

Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device

Semiconductor device having a grain orientation layer

Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region

Enhanced transistor performance of N-channel transistors by using an additional layer above a dual stress liner in a semiconductor device

SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME

Technique for enhancing transistor performance by transistor specific contact design

Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategies

FIELD EFFECT TRANSISTOR HAVING AN INTERLAYER DIELECTRIC MATERIAL HAVING INCREASED INTRINSIC STRESS

METHOD OF FORMING A METAL LAYER OVER A PATTERNED DIELECTRIC BY ELECTROLESS DEPOSITION USING A SELECTIVELY PROVIDED ACTIVATION LAYER

Method for reducing etch-induced process uniformities by omitting deposition of an endpoint detection layer during patterning of stressed overlayers in a semiconductor device

Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device

Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor device

Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device

Arc layer having a reduced flaking tendency and a method of manufacturing the same

Method of reducing contamination by providing a removable polymer protection film during microstructure processing

Technique for non-destructive metal delamination monitoring in semiconductor devices

Method of increasing the etch selectivity in a contact structure of semiconductor devices

Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process

Method of reducing contamination by providing an etch stop layer at the substrate edge

Semiconductor device comprising a contact structure with increased etch selectivity

Technique for increasing adhesion of metallization layers by providing dummy vias