Milpitas, California
United States
51
2026-05-28
The entities that hold a legal rights for patent applications filed by inventor Li Juane:
Juane Li from Milpitas, US has applied for patents for these inventions. The list has both pending applications and granted patents:
TRACKING HOST-PROVIDED METADATA IN A MEMORY SUB-SYSTEM
#2 | 2026-04-23DETECTING MEMORY READ ERRORS BY TRIGGERING MORE WORD LINE SCANS IF NEEDED
#3 | 2026-03-05EARLY USE OF RAIN IN READ ERROR HANDLING PROCESS
#4 | 2026-03-05SYSTEM FOR GENERATING VIRTUAL BLOCK STRIPES IN A MEMORY DEVICE
#5 | 2026-02-26TEMPERATURE-ADAPTIVE SCAN FREQUENCY CONTROL FOR MEMORY DEVICE STATE MANAGEMENT
#6 | 2026-02-26SELECTIVE CODEWORD MEDIA SCAN SYSTEM
#7 | 2026-02-05HANDLING PROGRAM FAILURE IN ZONE MEMORY SYSTEM
#8 | 2026-02-05HANDLING READ FAILURE IN ZONE MEMORY SYSTEM
#9 | 2026-02-05HANDLING READ-VERIFY FAILURE IN ZONE MEMORY SYSTEM
#10 | 2026-01-15REDUNDANT ARRAY OF INDEPENDENT NOT-AND (RAIN) BLOCK RETIREMENT HANDLING
#11 | 2025-11-20EMPTY PAGE SCAN OPERATIONS IMPROVEMENT
#12 | 2025-11-06WEAR LEVELING IN A ZONED NAMESPACE MEMORY SUB-SYSTEM
#13 | 2025-11-06BLOCK SET GROUPING POLICY IN A ZONED NAMESPACE MEMORY SUB-SYSTEM
#14 | 2025-08-14DYNAMIC PARTITION COMMAND QUEUES FOR A MEMORY DEVICE
#15 | 2025-07-17CRYPTOGRAPHIC KEY MANAGEMENT
#16 | 2025-06-05MEMORY DEVICE WITH FAST WRITE MODE TO MITIGATE POWER LOSS
#17 | 2025-03-13CRYPTOGRAPHIC KEY MANAGEMENT
#18 | 2024-06-20OPEN BLOCK MANAGEMENT IN MEMORY DEVICES
#19 | 2024-05-02REDUCE READ COMMAND LATENCY IN PARTITION COMMAND SCHEDULING AT A MEMORY DEVICE
#20 | 2024-04-18Concurrent command limiter for a memory system
#21 | 2024-03-07Dynamic partition command queues for a memory device
#22 | 2024-02-29EFFICIENT PERIODIC BACKEND REFRESH READS FOR REDUCING BIT ERROR RATE IN MEMORY DEVICES
#23 | 2024-02-29REDUCING BIT ERROR RATE IN MEMORY DEVICES
#24 | 2024-02-22READ VERIFICATION CADENCE AND TIMING IN MEMORY DEVICES
#25 | 2024-02-22Open block management in memory devices
#26 | 2024-02-08Memory device with fast write mode to mitigate power loss
#27 | 2023-12-21ENABLING STRIPE-BASED OPERATIONS FOR ERROR RECOVERY AT A MEMORY SUB-SYSTEM
#28 | 2023-08-10Tracking host-provided metadata in a memory sub-system
#29 | 2023-08-03Cryptographic key management
#30 | 2023-03-16PARITY DATA MODIFICATION FOR PARTIAL STRIPE DATA UPDATE
#31 | 2023-03-02Using P2L mapping table to manage move operation
#32 | 2023-03-02Tracking host-provided metadata in a memory sub-system
#33 | 2023-03-02Redundancy metadata media management at a memory sub-system
#34 | 2023-03-02Read-modify-write data consistency management
#35 | 2023-03-02Media access operation command management using media buffers
#36 | 2023-03-02Concurrent command limiter for a memory system
#37 | 2023-03-02Enabling stripe-based operations for error recovery at a memory sub-system
#38 | 2023-02-23Partition command queues for a memory device
#39 | 2023-02-23Managing package switching based on switching parameters
#40 | 2023-02-23Dynamic partition command queues for a memory device
#41 | 2023-02-23Reduce read command latency in partition command scheduling at a memory device
#42 | 2022-03-31Performing error checking operations on encrypted write data in a memory sub-system
#43 | 2022-03-31Performing scrambling operations based on a physical block address of a memory sub-system
#44 | 2021-12-02Storage error correction using cyclic-code based LDPC codes
#45 | 2021-11-04Generating error checking data for error detection during modification of data in a memory sub-system
#46 | 2021-09-02Generating error checking data for error detection during modification of data in a memory sub-system
#47 | 2021-01-21Cryptographic key management
#48 | 2021-01-14Generating error checking data for error detection during modification of data in a memory sub-system
#49 | 2021-01-14Generating error checking data for error detection during modification of data in a memory sub-system
#50 | 2019-11-07Error correction using cyclic code-based LDPC codes
#51 | 2017-05-25Error correction using cyclic code-based LDPC codes
1887544 ⎘