Inventor profile of:

David J. Widiger

City:

Pflugerville, Texas

Country:

United States

Published Applications:

18

Last publication date:

2025-07-31

Top Assignees for applications by David J. Widiger

The entities that hold a legal rights for patent applications filed by inventor Widiger David J.:

Recent patent applications by Widiger David J.

David J. Widiger from Pflugerville, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-07-31
US20250245411A1
Physics

WIRING PATTERN-BASED PARASITIC CAPACITANCE EXTRACTION

#2 | 2025-05-15
US20250156622A1
Physics

PROCESS OF FITTING FUNCTION PARAMETERS THAT FACILITATES ACCURATE PATTERN-BASED 3D CAPACITANCE EXTRACTION

#3 | 2022-02-03
US20220035983A1
Physics

Capacitance extraction

#4 | 2021-11-16
US16906874
Physics

Extracting parasitic capacitance from circuit designs

#5 | 2020-12-10
US20200387580A1
Physics

Selectively grounding fill wires

#6 | 2020-04-30
US20200134129A1
Physics

Capacitance extraction for floating metal in integrated circuit

#7 | 2017-07-20
US20170206299A1
Physics

Method for improving capacitance extraction performance by approximating the effect of distant shapes

#8 | 2017-06-22
US20170177776A1
Physics

PARTITIONING OF WIRING FOR CAPACITANCE EXTRACTION WITHOUT LOSS IN ACCURACY

#9 | 2017-06-15
US20170169151A1
Physics

Methods and computer program products for via capacitance extraction

#10 | 2017-06-08
US20170161422A1
Physics

Process for improving capacitance extraction performance

#11 | 2012-07-19
US20120185815A1
Physics

Method for extracting information for a circuit design

#12 | 2012-07-12
US20120180013A1
Physics

Method for extracting information for a circuit design

#13 | 2011-03-31
US20110078642A1
Physics

Method for calculating capacitance gradients in VLSI layouts using a shape processing engine

#14 | 2010-10-14
US20100262940A1
Physics

Accurate approximation of resistance in a wire with irregular biasing and determination of interconnect capacitances in VLSI layouts in the presence of Catastrophic Optical Proximity Correction

#15 | 2010-09-30
US20100251198A1
Physics

Method for extracting information for a circuit design

#16 | 2009-03-19
US20090077515A1
Physics

Method of constrained aggressor set selection for crosstalk induced noise

#17 | 2007-01-11
US20070011630A1
Physics

Methods for computing Miller-factor using coupled peak noise

#18 | 2006-08-24
US20060190881A1
Physics

Method for estimating propagation noise based on effective capacitance in an integrated circuit chip

InventorID:

1897486 ⎘