Juergen Pille

DYNAMIC ADJUSTMENT OF SIGNAL DELAY WITH MEMORY ARRAY VOLTAGE

Erasing a partition of an SRAM array with hardware support

Semiconductor circuit including an initialization circuit for initializing memory cells and clearing of relatively large blocks of memory

Integrated circuit including logic circuitry

Stressing integrated circuits using a radiation source

Buried conductive layer supplying digital circuits

Microelectronic device with a memory element utilizing stacked vertical devices

Integrated circuit with vertical structures on nodes of a grid

Microelectronic device utilizing stacked vertical devices

Memory block erasure

Memory block erasure

ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT

Activation of memory core circuits in an integrated circuit

Activation of memory core circuits in an integrated circuit

Activation of memory core circuits in an integrated circuit

Current-mode sense amplifier

Automated stressing and testing of semiconductor memory cells

Current-mode sense amplifier

Automated stressing and testing of semiconductor memory cells

Stressing and testing semiconductor memory cells

Single ended bitline current sense amplifier for SRAM applications

Current-mode sense amplifier

Current-mode sense amplifier

Current-mode sense amplifier

Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages

Advanced array local clock buffer base block circuit

Advanced Array Local Clock Buffer Base Block Circuit

Boost circuit for generating an adjustable boost voltage

Method and system for pipeline reduction

Progamable control clock circuit for arrays

Test interface for memory elements

Functional float mode screen to test for leakage defects on SRAM bitlines

Method to reduce leakage of a SRAM-array

Low power programmable clock delay generator with integrated decode function

Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuit

Level shifter for boosting wordline voltage and memory cell performance

Single-ended read and differential write scheme

Layout Generator for Routing and Designing an LSI

Redundancy in signal distribution trees

Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuit

6 Transistor Memory Circuit Pair Supporting Simultaneous Read/Write and Method Therefore

Wordline booster design structure and method of operating a wordine booster circuit

Wordline booster circuit and method of operating a wordline booster circuit

Automatic check for cyclic operating conditions for SOI circuit simulation

Random access memory with a plurality of symmetrical memory cells

Methods and apparatus for accessing memory

Redundancy in signal distribution trees

AUTOMATIC ADDITION OF POWER CONNECTIONS TO CHIP POWER

Memory array with multiple read ports

Automatic method for routing and designing an LSI

Device and method for decoding an address word into word-line signals

Power saving by disabling cyclic bitline precharge

Device and method for decoding an address word into word-line signals