ROBERT A. CORDES

CLEAR PREFETCH STREAM ON DETECTION OF PIPELINE FLUSH

Writing store data of multiple store operations into a cache line in a single cycle

Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges

Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations

Handling oversize store to load forwarding in a processor

FUSION OF MICROPROCESSOR STORE INSTRUCTIONS

INSTRUCTION AGE MATRIX AND LOGIC FOR QUEUES IN A PROCESSOR

Handling unaligned load operations in a multi-slice computer processor

Handling unaligned load operations in a multi-slice computer processor

Handling unaligned load operations in a multi-slice computer processor

Handling unaligned load operations in a multi-slice computer processor

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Extended store forwarding for store misses without cache allocate

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

Operation of a multi-slice processor implementing simultaneous two-target loads and stores

Operation of a multi-slice processor implementing simultaneous two-target loads and stores

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor

Handling unaligned load operations in a multi-slice computer processor

Handling unaligned load operations in a multi-slice computer processor

Dependency matrix with reduced area and power consumption