Inventor profile of:

Debapriya CHATTERJEE

City:

Austin, Texas

Country:

United States

Published Applications:

24

Last publication date:

2024-02-22

Top Assignees for applications by Debapriya CHATTERJEE

The entities that hold a legal rights for patent applications filed by inventor CHATTERJEE Debapriya:

Recent patent applications by CHATTERJEE Debapriya

Debapriya CHATTERJEE from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-02-22
US20240061961A1
Physics

HARDWARE-BASED IMPLEMENTATION OF SECURE HASH ALGORITHMS

#2 | 2024-02-15
US20240053989A1
Physics

Hardware-based message block padding for hash algorithms

#3 | 2024-02-15
US20240053963A1
Physics

HARDWARE-BASED GALOIS MULTIPLICATION

#4 | 2024-01-25
US20240028772A1
Physics

Systems and methods for dynamic control of a secure mode of operation in a processor

#5 | 2024-01-11
US20240015004A1
Electricity

HARDWARE-BASED KEY GENERATION AND STORAGE FOR CRYPTOGRAPHIC FUNCTION

#6 | 2023-02-09
US20230040900A1
Physics

Secure memory isolation for secure endpoints

#7 | 2022-06-16
US20220191020A1
Electricity

Comparing hash values computed at function entry and exit for increased security

#8 | 2022-06-16
US20220188464A1
Physics

Systems and methods for dynamic control of a secure mode of operation in a processor

#9 | 2022-06-16
US20220188463A1
Physics

Method and system for on demand control of hardware support for software pointer authentification in a computing system

#10 | 2021-08-12
US20210247982A1
Physics

Dynamic modification of instructions that do not modify the architectural state of a processor

#11 | 2021-03-25
US20210089382A1
Physics

Software-invisible interrupt for a microprocessor

#12 | 2021-03-25
US20210089340A1
Physics

Obscuring information in virtualization environment

#13 | 2021-03-18
US20210081296A1
Physics

Identifying translation errors

#14 | 2021-01-21
US20210019262A1
Physics

Address translation cache invalidation in a microprocessor

#15 | 2020-11-26
US20200371951A1
Physics

Address translation cache invalidation in a microprocessor

#16 | 2020-11-19
US20200364313A1
Physics

Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation

#17 | 2020-07-16
US20200225952A1
Physics

Method and system for detection of thread stall

#18 | 2020-06-25
US20200201767A1
Physics

System and method including broadcasting an address translation invalidation instruction with a return marker to indentify the location of data in a computing system having mutiple processors

#19 | 2020-04-16
US20200117766A1
Physics

Precise verification of a logic problem on a simulation accelerator

#20 | 2019-06-27
US20190196816A1
Physics

Method and system for detection of thread stall

#21 | 2018-05-03
US20180120379A1
Physics

Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment

#22 | 2018-03-01
US20180059182A1
Physics

Circuit design verification in a hardware accelerated simulation environment using breakpoints

#23 | 2017-08-29
US15339314
Physics

Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment

#24 | 2017-06-22
US20170176529A1
Physics

Circuit design verification in a hardware accelerated simulation environment using breakpoints

InventorID:

1910369 ⎘