Inventor profile of:

Jason Eugene STEPHENS

City:

Menands, New York

Country:

United States

Published Applications:

12

Last publication date:

2018-08-09

Top Assignees for applications by Jason Eugene STEPHENS

The entities that hold a legal rights for patent applications filed by inventor STEPHENS Jason Eugene:

Recent patent applications by STEPHENS Jason Eugene

Jason Eugene STEPHENS from Menands, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-08-09
US20180226294A1
Electricity

Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias

#2 | 2018-02-01
US20180033701A1
Electricity

Methods, apparatus and system for a passthrough-based architecture

#3 | 2017-12-26
US15362035
Electricity

Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit

#4 | 2017-11-14
US15271497
Electricity

Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines

#5 | 2017-11-14
US15271475
Electricity

Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines

#6 | 2017-11-07
US15175495
Electricity

Interconnect structure for semiconductor devices with multiple power rails and redundancy

#7 | 2017-10-26
US20170309560A1
Electricity

Devices and methods for forming cross coupled contacts

#8 | 2017-10-10
US15271519
Electricity

Method of forming ANA regions in an integrated circuit

#9 | 2017-09-28
US20170278720A1
Electricity

Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit

#10 | 2017-09-14
US20170263506A1
Electricity

Methods, apparatus and system for a passthrough-based architecture

#11 | 2017-08-31
US20170250080A1
Electricity

Compensating for lithographic limitations in fabricating semiconductor interconnect structures

#12 | 2017-06-27
US15077384
Electricity

Method of forming a pattern for interconnection lines in an integrated circuit wherein the pattern includes gamma and beta block mask portions

InventorID:

1972972 ⎘