Dresden
Germany
25
2019-04-11
The entities that hold a legal rights for patent applications filed by inventor Gerhardt Martin:
Martin Gerhardt from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Transistor element with reduced lateral electrical field
#2 | 2018-12-13Heat dissipative element for polysilicon resistor bank
#3 | 2018-06-07Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell
#4 | 2017-11-16Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereof
#5 | 2016-04-07OPC enlarged dummy electrode to eliminate ski slope at eSiGe
#6 | 2015-11-26Transistor devices with high-k insulation layers
#7 | 2014-09-18Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages
#8 | 2014-03-13INTEGRATED CIRCUITS HAVING BORON-DOPED SILICON GERMANIUM CHANNELS AND METHODS FOR FABRICATING THE SAME
#9 | 2014-01-30Methods of forming transistor devices with high-k insulation layers and the resulting devices
#10 | 2013-04-18Methods of Forming Source/Drain Regions on Transistor Devices
#11 | 2012-09-27Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation
#12 | 2011-09-15Method for forming a strained transistor by stress memorization based on a stressed implantation mask
#13 | 2011-09-08Technique for enhancing transistor performance by transistor specific contact design
#14 | 2011-06-30Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy
#15 | 2010-02-25METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED STRESSOR AND EXTENSION REGIONS
#16 | 2008-12-09Methods for fabricating a stressed MOS device
#17 | 2008-12-04Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region
#18 | 2008-10-30Technique for enhancing transistor performance by transistor specific contact design
#19 | 2008-07-31Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device
#20 | 2008-03-25Methods for fabricating a CMOS device including silicide contacts
#21 | 2008-01-31Method for forming a strained transistor by stress memorization based on a stressed implantation mask
#22 | 2008-01-31Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography
#23 | 2007-12-06Method of increasing transistor drive current by recessing an isolation trench
#24 | 2007-10-04METHOD FOR FORMING ULTRA-SHALLOW HIGH QUALITY JUNCTIONS BY A COMBINATION OF SOLID PHASE EPITAXY AND LASER ANNEALING
#25 | 2006-01-05Technique for transferring strain into a semiconductor region
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