Taichung
Taiwan
62
2024-08-15
The entities that hold a legal rights for patent applications filed by inventor CHENG Chiting:
Chiting CHENG from Taichung, TW has applied for patents for these inventions. The list has both pending applications and granted patents:
VOLTAGE REGULATOR WITH POWER RAIL TRACKING
#2 | 2024-06-20Power detection circuit
#3 | 2024-03-07Pre-charging bit lines through charge-sharing
#4 | 2023-06-29Power detection circuit
#5 | 2023-06-15Voltage regulator with power rail tracking
#6 | 2022-07-28Configurable memory storage system
#7 | 2022-03-17Voltage regulator with power rail tracking
#8 | 2022-01-27Power detection circuit
#9 | 2021-07-29Voltage regulator with power rail tracking
#10 | 2021-07-01Configurable memory storage system
#11 | 2020-12-24Pre-charging bit lines through charge-sharing
#12 | 2020-12-10Leakage pathway prevention in a memory storage device
#13 | 2020-07-23Dual rail memory, memory macro and associated hybrid power supply method
#14 | 2020-06-18Clock circuit and method of operating the same
#15 | 2020-06-04Memory system having write assist circuit including memory-adapted transistors
#16 | 2020-06-04Memory macro and method of operating the same
#17 | 2020-04-30Boost schemes for write assist
#18 | 2020-03-12Configurable memory storage system
#19 | 2020-01-16Dual rail device with power detector
#20 | 2020-01-02Leakage pathway prevention in a memory storage device
#21 | 2019-11-14Pre-charging bit lines through charge-sharing
#22 | 2019-10-03Bit line logic circuits and methods
#23 | 2019-08-22Memory macro and method of operating the same
#24 | 2019-06-06Dual rail device with power detector
#25 | 2019-04-18Dual rail memory with bist circuitry, memory macro and associated hybrid power supply method
#26 | 2019-04-04Clock circuit and method of operating the same
#27 | 2019-01-31Clock generating circuit and method of operating the same
#28 | 2019-01-03Configurable memory storage system
#29 | 2018-12-06Maximum voltage selection circuit
#30 | 2018-10-18Device having write assist circuit including memory-adapted transistors and method for making the same
#31 | 2018-10-11Memory macro and method of operating the same
#32 | 2018-09-27Level shifter with improved voltage difference
#33 | 2018-06-21Pre-charging bit lines through charge-sharing
#34 | 2018-06-21Dual rail device with power detector for controlling power to first and second power domains
#35 | 2018-02-22Memory macro and method of operating the same
#36 | 2018-02-08Pre-charging bit lines through charge-sharing
#37 | 2017-09-28Memory macro and method of operating the same
#38 | 2017-09-14Level shifter circuit using boosting circuit
#39 | 2017-08-24Dual rail memory, memory macro and associated hybrid power supply method
#40 | 2017-05-25SRAM device capable of working in multiple low voltages without loss of performance
#41 | 2017-04-20Dual rail memory, memory macro and associated hybrid power supply method
#42 | 2017-03-23Dual rail memory, memory macro and associated hybrid power supply method
#43 | 2017-02-28SRAM device capable of working in multiple low voltages without loss of performance
#44 | 2017-02-09Power management circuit for an electronic device
#45 | 2015-09-24Memory unit and method of testing the same
#46 | 2015-09-17Negative bitline boost scheme for SRAM write-assist
#47 | 2015-09-03Memory reading circuit, memory device and method of operating memory device
#48 | 2015-05-14SPSRAM wrapper
#49 | 2015-05-14Negative bitline boost scheme for SRAM write-assist
#50 | 2015-04-30High density memory structure
#51 | 2015-04-30Memory device and a method of operating the same
#52 | 2014-08-21Write assist circuit, memory device and method
#53 | 2014-07-31Voltage divider control circuit
#54 | 2013-11-07Memory cell having flexible read/write assist and method of using
#55 | 2013-05-16Word line driver cell layout for SRAM and other semiconductor devices
#56 | 2013-04-25Method and apparatus for word line suppression
#57 | 2013-04-18Bit line voltage bias for low power memory design
#58 | 2013-03-21Efficient semiconductor device cell layout utilizing underlying local connective features
#59 | 2013-02-28Fly-over conductor segments in integrated circuits with successive load devices along a signal path
#60 | 2012-12-06SRAM read and write assist apparatus
#61 | 2012-11-15SRAM write assist apparatus
#62 | 2012-07-26Memory with word-line segment access
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