Arnold Ginetti

Method and system to implement altitude based I/O re-layering for electronic and photonic designs

Method and system to facilitate review of schematics for an electronic design

METHOD AND SYSTEM TO FACILITATE REVIEW OF SCHEMATICS FOR AN ELECTRONIC DESIGN

Methods, systems, and computer program product for implementing legal routing tracks across virtual hierarchies and legal placement patterns

System, method, and computer program product for displaying bump layout for manufacturing variations

Electronic circuit design editor with overlay of layout and schematic design features

Systems and methods for dynamically generating hierarchical rotating pcells from a static integrated circuit design

Technology database independent components for integrated circuit package

Methods and systems for schematic driven 2D chaining in an integrated circuit layout

Methods, systems, and computer program product for implementing an electronic design by manipulating a hierarchical structure of the electronic design

Method and system for performing incremental post layout simulation with layout edits

Methods, systems, and computer program product for implementing virtual prototyping for electronic designs

Methods, systems, and computer program product for implementing legal routing tracks across virtual hierarchies and legal placement patterns

Method and apparatus to drive layout of arbitrary EM-coil through parametrized cell

Methods, systems, and computer program product for dynamically abstracting virtual hierarchies for an electronic design

Methods, systems, and computer program product for implementing dynamic maneuvers within virtual hierarchies of an electronic design

Methods, systems, and computer program product for implementing three-dimensional integrated circuit designs

Methods, systems, and computer program product for implementing synchronous clones for an electronic design

Methods, systems, and computer program product for implementing a floorplan with virtual hierarchies and figure groups for an electronic design

Methods, systems, and computer program product for implementing engineering change orders with figure groups and virtual hierarchies

Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design

Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awareness

Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabrics

Methods and systems for enabling concurrent editing of electronic circuit layouts

Methods and systems for generation and editing of parameterized figure group

Methods, systems, and computer program product for implementing a simulation platform with dynamic device model libraries for electronic designs

Methods, systems, and computer program product for implementing electronic design layouts with symbolic representations

System and method for accelerated graphic rendering of design layout having variously sized geometric objects

Method, system, and computer program product for implementing a multi-fabric electronic design spanning across multiple design fabrics

Method, system, and computer program product for probing or netlisting a multi-fabric electronic design spanning across multiple design fabrics

Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabrics

Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabrics

System and method to drag instance master physical shell

System and method for automatically reconfiguring chain of abutted devices in electronic circuit design

System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters

Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design

Method and apparatus for circuit simulation using parallel computing

SYNCHRONIZED THREE-DIMENSIONAL DISPLAY OF CONNECTED DOCUMENTS

Synchronized three-dimensional display of connected documents

Change tracking and incremental synchronization of EDA design and technology data

Method and system for implementing graphically editable parameterized cells

System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters

Method to preview an undo/redo list

Systems and methods of editing cells of an electronic circuit design

Method, system, and computer program product for implementing multi-power domain digital / mixed signal verification and low power simulation

Method, system, and computer program product for implementing multi-power domain digital / mixed-signal verification and low power simulation

System to merge custom and synthesized digital integrated circuit design data

Method and system for implementing abstract layout structures with parameterized cells

Method and system for implementing graphically editable parameterized cells

System and method for generating flat layout

Method and system for implementing multiuser cached parameterized cells

Method for updating a placed and routed netlist

Method and apparatus for maintaining synchronization between layout clones

Method and system for implementing cached parameterized cells