Northborough, Massachusetts
United States
50
2025-01-28
The entities that hold a legal rights for patent applications filed by inventor Kessler Richard E.:
Richard E. Kessler from Northborough, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Processor data cache with shared mid-level cache and low-level cache
#2 | 2021-07-01Method and apparatus for managing global chip power on a multicore system on chip
#3 | 2021-03-18Secure low-latency chip-to-chip communication
#4 | 2020-10-22Limiting backpressure with bad actors
#5 | 2020-09-24Method and apparatus for managing global chip power on a multicore system on chip
#6 | 2017-10-26Method and apparatus for dynamic virtual system on chip
#7 | 2017-08-10Method and apparatus for managing global chip power on a multicore system on chip
#8 | 2017-07-20Collapsed address translation with multiple page sizes
#9 | 2016-10-27Method for work scheduling in a multi-chip system
#10 | 2016-05-19Programmable validation of transaction requests
#11 | 2016-05-19Arbitrated access to resources among multiple devices
#12 | 2016-05-19Register access control among multiple devices
#13 | 2016-05-19Programmable ordering and prefetch
#14 | 2016-05-19Independent Ordering Of Independent Transactions
#15 | 2015-10-08Messaging with flexible transmit ordering
#16 | 2015-09-17METHOD AND APPARATUS FOR LOW LATENCY EXCHANGE OF DATA BETWEEN A PROCESSOR AND COPROCESSOR
#17 | 2015-09-10Method and system for ordering I/O access in a multi-node environment
#18 | 2015-09-10Inter-chip interconnect protocol for a multi-chip system
#19 | 2015-09-10MULTI-CORE NETWORK PROCESSOR INTERCONNECT WITH MULTI-NODE CONNECTION
#20 | 2015-09-10Method and system for work scheduling in a multi-chip system
#21 | 2015-09-10Method and apparatus for memory allocation in a multi-node system
#22 | 2015-09-03Packet shaping in a network processor
#23 | 2015-09-03Packet scheduling in a network processor
#24 | 2015-09-03Packet output processing
#25 | 2015-06-18DRAM address protection
#26 | 2015-04-09Method and apparatus for supporting wide operations using atomic sequences
#27 | 2015-04-09Method and apparatus for conditional storing of data using a compare-and-swap based approach
#28 | 2015-03-26Method and apparatus for managing global chip power on a multicore system on chip
#29 | 2015-03-26Collapsed address translation with multiple page sizes
#30 | 2015-03-26Translation bypass in multi-stage address translation
#31 | 2015-03-26Maintenance of cache and tags in a translation lookaside buffer
#32 | 2015-03-26Merged TLB structure for multiple sequential address translations
#33 | 2015-01-08Method and apparatus for power control
#34 | 2014-12-18System and method to provide non-coherent access to a coherent memory system
#35 | 2014-10-23Method and apparatus for managing write back cache
#36 | 2014-03-20Messaging with flexible transmit ordering
#37 | 2014-01-09System and method to reduce memory access latencies using selective replication across multiple memory ports
#38 | 2013-10-24Input output bridging
#39 | 2013-09-26Hardware and Software Association and Authentication
#40 | 2013-05-02Multi-core interconnect in a network processor
#41 | 2013-05-02Network processor with distributed trace buffers
#42 | 2013-05-02Packet traffic control in a network processor
#43 | 2013-04-25Method and apparatus for power control
#44 | 2013-04-25System and method to provide non-coherent access to a coherent memory system
#45 | 2013-04-25System and method to reduce memory access latencies using selective replication across multiple memory ports
#46 | 2013-04-25Input output bridging
#47 | 2013-04-25Packet priority in a network processor
#48 | 2013-04-18Processor with efficient work queuing
#49 | 2012-07-19DRAM address protection
#50 | 2012-06-21Messaging with flexible transmit ordering
201922 ⎘