AUSTIN, Texas
United States
24
2018-12-20
The entities that hold a legal rights for patent applications filed by inventor LEVENSTEIN SHELDON B.:
SHELDON B. LEVENSTEIN from AUSTIN, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Dynamic sequential instruction prefetching
#2 | 2017-11-16Techniques for dynamic sequential instruction prefetching
#3 | 2012-11-22Method for detecting address match in a deeply pipelined processor design
#4 | 2012-07-05Controlling power of a cache based on predicting the instruction cache way for high power applications
#5 | 2009-08-06Branch target address cache with hashed indices
#6 | 2008-10-23System and method for tracking changes in L1 data cache directory
#7 | 2008-08-28Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch
#8 | 2008-07-03System for generating effective address
#9 | 2008-05-01Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream
#10 | 2008-01-10Method and apparatus for efficiently accessing both aligned and unaligned data from a memory
#11 | 2006-08-17Method, apparatus and program product for enhancing performance of an in-order processor with long stalls
#12 | 2006-08-17Mini-refresh processor recovery as bug workaround method using existing recovery hardware
#13 | 2006-08-17Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor
#14 | 2006-08-17Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch
#15 | 2006-08-17Method and apparatus for efficiently accessing both aligned and unaligned data from a memory
#16 | 2006-08-10System and method for generating effective address
#17 | 2006-08-10Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream
#18 | 2006-08-10Method for detecting address match in a deeply pipelined processor design
#19 | 2006-08-10Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class
#20 | 2006-08-10System and method for tracking changes in L1 data cache directory
#21 | 2006-04-20Processor, data processing system and method for synchronzing access to data in shared memory
#22 | 2006-04-20Processor, data processing system and method for synchronizing access to data in shared memory
#23 | 2006-04-20Processor, data processing system and method for synchronizing access to data in shared memory
#24 | 2006-01-05Apparatus and method for detecting multiple hits in CAM arrays
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