Inventor profile of:

Pradip Patel

City:

Poughkeepsie, New York

Country:

United States

Published Applications:

19

Last publication date:

2021-03-11

Top Assignees for applications by Pradip Patel

The entities that hold a legal rights for patent applications filed by inventor Patel Pradip:

Recent patent applications by Patel Pradip

Pradip Patel from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2021-03-11
US20210074376A1
Physics

Built-in self-test for bit-write enabled memory arrays

#2 | 2021-03-11
US20210074375A1
Physics

Sequential error capture during memory test

#3 | 2021-01-12
US16559776
Physics

Power saving scannable latch output driver

#4 | 2018-06-21
US20180174666A1
Physics

Testing content addressable memory and random access memory

#5 | 2018-05-31
US20180151248A1
Physics

Testing content addressable memory and random access memory

#6 | 2018-04-26
US20180114585A1
Physics

Testing content addressable memory and random access memory

#7 | 2017-12-07
US20170350940A1
Physics

Partition-able storage of test results using inactive storage elements

#8 | 2017-07-04
US15084639
Physics

Multi-match error detection in content addressable memory testing

#9 | 2017-04-18
US15197271
Physics

Shift register with opposite shift data and shift clock directions

#10 | 2011-12-15
US20110307747A1
Physics

Memory testing system

#11 | 2011-12-01
US20110296259A1
Physics

TESTING MEMORY ARRAYS AND LOGIC WITH ABIST CIRCUITRY

#12 | 2009-08-13
US20090204762A1
Physics

Self test apparatus for identifying partially defective memory

#13 | 2008-03-06
US20080059854A1
Physics

Merged MISR and output register without performance impact for circuits under test

#14 | 2006-09-14
US20060203578A1
Physics

Method for self-correcting cache using line delete, data logging, and fuse repair correction

#15 | 2006-08-31
US20060195740A1
Physics

Clock duty cycle based access timer combined with standard stage clocked output register

#16 | 2006-08-31
US20060195738A1
Physics

Merged MISR and output register without performance impact for circuits under test

#17 | 2006-08-03
US20060174175A1
Physics

Array self repair using built-in self test techniques

#18 | 2006-07-13
US20060156130A1
Physics

Self test method and apparatus for identifying partially defective memory

#19 | 2005-12-01
US20050268167A1
Physics

BIST address generation architecture for multi-port memories

InventorID:

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