Sharon, Massachusetts
United States
29
2026-06-18
The entities that hold a legal rights for patent applications filed by inventor Lerner Boris:
Boris Lerner from Sharon, US has applied for patents for these inventions. The list has both pending applications and granted patents:
DISTRIBUTION GRID AWARENESS
#2 | 2024-11-14MODULAR INTERNAL BATTERY TEMPERATURE ESTIMATION TECHNIQUES
#3 | 2023-07-13PERSONALIZED AUDIO ZONE VIA A COMBINATION OF ULTRASONIC TRANSDUCERS AND LOW-FREQUENCY SPEAKER
#4 | 2021-05-20AUDIO SYSTEM SPEAKER VIRTUALIZATION
#5 | 2020-10-29Optical system for determining interferer locus among two or more regions of a transmissive liquid crystal structure
#6 | 2019-09-26Current measurement using magnetic sensors and contour intervals
#7 | 2017-08-03Fixed-point high dynamic range fast fourier transforms
#8 | 2017-04-06Scaling fixed-point fast Fourier transforms in radar and sonar applications
#9 | 2016-08-25DOWNSAMPLING BY AVERAGING WITH REDUCED MEMORY REQUIREMENTS
#10 | 2016-02-04TRACKING SLOW VARYING FREQUENCY IN A NOISY ENVIRONMENT AND APPLICATIONS IN HEALTHCARE
#11 | 2015-06-04Thread offset counter
#12 | 2015-05-28METHODS AND APPARATUS FOR IMAGE PROCESSING AT PIXEL RATE
#13 | 2014-11-20Parallel atomic increment
#14 | 2014-09-18FFT accelerator
#15 | 2014-04-24Predicate counter
#16 | 2014-04-24MEMORY ARCHITECTURE
#17 | 2014-04-24Memory interconnect network architecture for vector processor
#18 | 2013-12-26Methods and apparatus for image processing at pixel rate
#19 | 2013-12-12Downsampling with partial-sum re-use
#20 | 2013-09-26Methods and apparatus for image processing at pixel rate
#21 | 2013-05-02DMA CONTROL OF A DYNAMICALLY RECONFIGURABLE PIPELINED PRE-PROCESSOR
#22 | 2013-04-25Dual control of a dynamically reconfigurable pipelined pre-processor
#23 | 2013-04-25FRAME-BY-FRAME CONTROL OF A DYNAMICALLY RECONFIGURABLE PIPELINED PRE-PROCESSOR
#24 | 2013-04-25DYNAMICALLY RECONFIGURABLE PIPELINED PRE-PROCESSOR
#25 | 2012-07-12Methods and apparatus for image processing at pixel rate
#26 | 2011-05-19Methods and apparatus for image processing at pixel rate
#27 | 2010-07-08Processor architectures for enhanced computational capability and low latency
#28 | 2010-02-11Computing module for efficient FFT and FIR hardware accelerator
#29 | 2005-06-28Method, apparatus, and product for use in generating CRC and other remainder based codes
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