Inventor profile of:

Boris Lerner

City:

Sharon, Massachusetts

Country:

United States

Published Applications:

29

Last publication date:

2026-06-18

Top Assignees for applications by Boris Lerner

The entities that hold a legal rights for patent applications filed by inventor Lerner Boris:

Recent patent applications by Lerner Boris

Boris Lerner from Sharon, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-06-18
US20260169043A1
Physics

DISTRIBUTION GRID AWARENESS

#2 | 2024-11-14
US20240377462A1
Physics

MODULAR INTERNAL BATTERY TEMPERATURE ESTIMATION TECHNIQUES

#3 | 2023-07-13
US20230224639A1
Electricity

PERSONALIZED AUDIO ZONE VIA A COMBINATION OF ULTRASONIC TRANSDUCERS AND LOW-FREQUENCY SPEAKER

#4 | 2021-05-20
US20210152939A1
Electricity

AUDIO SYSTEM SPEAKER VIRTUALIZATION

#5 | 2020-10-29
US20200341143A1
Physics

Optical system for determining interferer locus among two or more regions of a transmissive liquid crystal structure

#6 | 2019-09-26
US20190293689A1
Physics

Current measurement using magnetic sensors and contour intervals

#7 | 2017-08-03
US20170220522A1
Physics

Fixed-point high dynamic range fast fourier transforms

#8 | 2017-04-06
US20170097405A1
Physics

Scaling fixed-point fast Fourier transforms in radar and sonar applications

#9 | 2016-08-25
US20160246755A1
Physics

DOWNSAMPLING BY AVERAGING WITH REDUCED MEMORY REQUIREMENTS

#10 | 2016-02-04
US20160029968A1
Human necessities

TRACKING SLOW VARYING FREQUENCY IN A NOISY ENVIRONMENT AND APPLICATIONS IN HEALTHCARE

#11 | 2015-06-04
US20150154027A1
Physics

Thread offset counter

#12 | 2015-05-28
US20150147005A1
Physics

METHODS AND APPARATUS FOR IMAGE PROCESSING AT PIXEL RATE

#13 | 2014-11-20
US20140344545A1
Physics

Parallel atomic increment

#14 | 2014-09-18
US20140280421A1
Physics

FFT accelerator

#15 | 2014-04-24
US20140115302A1
Physics

Predicate counter

#16 | 2014-04-24
US20140115278A1
Physics

MEMORY ARCHITECTURE

#17 | 2014-04-24
US20140115224A1
Physics

Memory interconnect network architecture for vector processor

#18 | 2013-12-26
US20130342551A1
Physics

Methods and apparatus for image processing at pixel rate

#19 | 2013-12-12
US20130332495A1
Physics

Downsampling with partial-sum re-use

#20 | 2013-09-26
US20130249923A1
Physics

Methods and apparatus for image processing at pixel rate

#21 | 2013-05-02
US20130106871A1
Physics

DMA CONTROL OF A DYNAMICALLY RECONFIGURABLE PIPELINED PRE-PROCESSOR

#22 | 2013-04-25
US20130101053A1
Electricity

Dual control of a dynamically reconfigurable pipelined pre-processor

#23 | 2013-04-25
US20130100147A1
Physics

FRAME-BY-FRAME CONTROL OF A DYNAMICALLY RECONFIGURABLE PIPELINED PRE-PROCESSOR

#24 | 2013-04-25
US20130100146A1
Physics

DYNAMICALLY RECONFIGURABLE PIPELINED PRE-PROCESSOR

#25 | 2012-07-12
US20120176389A1
Physics

Methods and apparatus for image processing at pixel rate

#26 | 2011-05-19
US20110115804A1
Physics

Methods and apparatus for image processing at pixel rate

#27 | 2010-07-08
US20100174883A1
Physics

Processor architectures for enhanced computational capability and low latency

#28 | 2010-02-11
US20100036898A1
Physics

Computing module for efficient FFT and FIR hardware accelerator

#29 | 2005-06-28
US9788859
-

Method, apparatus, and product for use in generating CRC and other remainder based codes

InventorID:

206622 ⎘