Inventor profile of:

Jun Xu

City:

San Jose, California

Country:

United States

Published Applications:

26

Last publication date:

2026-01-29

Top Assignees for applications by Jun Xu

The entities that hold a legal rights for patent applications filed by inventor Xu Jun:

Recent patent applications by Xu Jun

Jun Xu from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-01-29
US20260031153A1
Physics

DATA LINE KNOCK OUT FOR POWER SAVING WHILE ACCESSING MEMORY CELLS

#2 | 2025-12-18
US20250384907A1
Physics

BIAS CURRENT GENERATION METHODS AND SYSTEMS FOR FAST CURRENT SENSING

#3 | 2025-09-25
US20250298065A1
Physics

REAL-TIME CIRCUIT LINE RESISTOR-CAPACITOR DETECTION

#4 | 2025-02-27
US20250071278A1
Electricity

BINARIZATION OF DQP USING SEPARATE ABSOLUTE VALUE AND SIGN (SAVS) IN CABAC

#5 | 2024-12-05
US20240404615A1
Physics

DEFECT DETECTION DURING ERASE OPERATIONS

#6 | 2024-02-29
US20240071531A1
Physics

MEMORY DEVICES WITH PROGRAM VERIFY LEVELS BASED ON COMPENSATION VALUES

#7 | 2023-08-17
US20230262219A1
Electricity

Binarization of dQP using Separate Absolute Value and Sign (SAVS) in CABAC

#8 | 2023-03-16
US20230078401A1
Physics

Managing programming convergence associated with memory cells of a memory sub-system

#9 | 2023-03-02
US20230067457A1
Physics

Defect detection during erase operations

#10 | 2023-03-02
US20230060943A1
Physics

MEMORY DEVICE DEFECT MANAGEMENT

#11 | 2023-01-19
US20230017995A1
Physics

Charge loss detection using a multiple sampling scheme

#12 | 2022-09-29
US20220310158A1
Physics

All levels dynamic start voltage programming of a memory device in a memory sub-system

#13 | 2022-09-15
US20220293182A1
Physics

Estimating resistance-capacitance time constant of electrical circuit

#14 | 2022-07-28
US20220238165A1
Physics

Memory cell sensing

#15 | 2022-07-19
US17175301
Physics

Estimating resistance-capacitance time constant of electrical circuit

#16 | 2022-06-09
US20220180952A1
Physics

Managing programming convergence associated with memory cells of a memory sub-system

#17 | 2022-05-05
US20220139465A1
Physics

Memory cell sensing

#18 | 2022-04-21
US20220124331A1
Electricity

Binarization of dQP using separate absolute value and sign (SAVS) in CABAC

#19 | 2021-01-21
US20210021839A1
Electricity

Extensions of motion-constrained tile sets SEI message for interactivity

#20 | 2021-01-21
US20210021829A1
Electricity

Binarization of DQP using separate absolute value and sign (SAVS) in CABAC

#21 | 2019-08-08
US20190246116A1
Electricity

Extensions of motion-constrained tile sets sei message for interactivity

#22 | 2018-07-05
US20180192052A1
Electricity

Binarization of DQP using separate absolute value and sign (SAVS) in CABAC

#23 | 2016-03-03
US20160065963A1
Electricity

BINARIZATION OF DQP USING SEPARATE ABSOLUTE VALUE AND SIGN (SAVS) IN CABAC

#24 | 2015-01-15
US20150016504A1
Electricity

Extensions of motion-constrained tile sets SEI message for interactivity

#25 | 2013-04-25
US20130101047A1
Electricity

CONTEXT REDUCTION OF SIGNIFICANCE MAP CODING OF 4X4 AND 8X8 TRANSFORM COEFFICIENT IN HM4.0

#26 | 2012-12-20
US20120320971A1
Electricity

Binarization of DQP using separate absolute value and sign (SAVS) in CABAC

InventorID:

208022 ⎘