Round Rock, Texas
United States
25
2022-02-03
The entities that hold a legal rights for patent applications filed by inventor Ja Yee:
Yee Ja from Round Rock, US has applied for patents for these inventions. The list has both pending applications and granted patents:
System and method for providing an intelligent ephemeral distributed service model for server group provisioning
#2 | 2021-05-06System and method for providing an intelligent ephemeral distributed service model for server group provisioning
#3 | 2020-06-04System and method for preventing well behaving clients from causing account lockouts in a group
#4 | 2019-08-08System and method for group of groups single sign-on demarcation based on first user login
#5 | 2019-08-08System and method for preventing well behaving clients from causing account lockouts in a group
#6 | 2019-08-08System and method for providing quality of service during transport key rotation at a distributed management controller group
#7 | 2018-01-18System and method for managing distributed cluster identity
#8 | 2009-05-28Sequential equivalence checking for asynchronous verification
#9 | 2009-05-21Driving values to DC adjusted/untimed nets to identify timing problems
#10 | 2008-12-04Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic
#11 | 2008-11-27Modeling asynchronous behavior from primary inputs and latches
#12 | 2008-10-30Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation
#13 | 2008-08-14Methods and arrangements to model an asynchronous interface
#14 | 2008-03-20Method for asynchronous clock modeling in an integrated circuit simulation
#15 | 2008-03-20Method for modeling metastability decay through latches in an integrated circuit model
#16 | 2008-02-14Accurately modeling an asynchronous interface using expanded logic elements
#17 | 2008-01-17Method for driving values to DC adjusted/untimed nets to identify timing problems
#18 | 2007-12-06Method for propagating phase constants in static model analysis of circuits
#19 | 2007-11-22Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation
#20 | 2007-11-01Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic
#21 | 2007-10-18METHOD FOR MODELING METASTABILITY DECAY USING FENCE LOGIC INSERTION
#22 | 2007-08-23Modeling asynchronous behavior from primary inputs and latches
#23 | 2007-05-03Methods and arrangements to model an asynchronous interface
#24 | 2006-08-24System and method for unfolding/replicating logic paths to facilitate propagation delay modeling
#25 | 2006-08-24System and method for accurately modeling an asynchronous interface using expanded logic elements
2095598 ⎘