Dresden
Germany
29
2017-01-05
The entities that hold a legal rights for patent applications filed by inventor Huisinga Torsten:
Torsten Huisinga from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Embedded metal-insulator-metal capacitor
#2 | 2016-04-07Method of forming an embedded metal-insulator-metal (MIM) capacitor
#3 | 2015-08-20Methods for fabricating integrated circuits including densifying interlevel dielectric layers
#4 | 2015-04-09Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
#5 | 2015-03-19INTEGRATED CIRCUITS WITH STRAINED SILICON AND METHODS FOR FABRICATING SUCH CIRCUITS
#6 | 2014-11-27METHOD INCLUDING A REMOVAL OF A HARDMASK FROM A SEMICONDUCTOR STRUCTURE AND RINSING THE SEMICONDUCTOR STRUCTURE WITH AN ALKALINE RINSE SOLUTION
#7 | 2014-09-18Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes
#8 | 2014-09-18Methods for forming protection layers on sidewalls of contact etch stop layers
#9 | 2014-08-28Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
#10 | 2014-07-17Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
#11 | 2013-11-14REDUCING LINE EDGE ROUGHNESS IN HARDMASK INTEGRATION SCHEMES
#12 | 2013-11-14REPLACEMENT GATE ELECTRODE FILL AT REDUCED TEMPERATURES
#13 | 2013-07-25METHODS OF FABRICATING INTEGRATED CIRCUITS WITH THE ELIMINATION OF VOIDS IN INTERLAYER DIELECTICS
#14 | 2013-07-11Methods of forming conductive structures using a dual metal hard mask technique
#15 | 2013-05-02Methods of Filling Voids in Copper Structures
#16 | 2013-04-25Methods of forming conductive structures in dielectric layers on an integrated circuit device
#17 | 2012-09-20ULTRAVIOLET (UV)-REFLECTING FILM FOR BEOL PROCESSING
#18 | 2012-09-06Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
#19 | 2012-08-09INTEGRATED CIRCUITS HAVING INTERCONNECT STRUCTURES AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING INTERCONNECT STRUCTURES
#20 | 2012-07-26Methods for fabricating semiconductor devices having local contacts
#21 | 2012-07-19Hybrid contact structure with low aspect ratio contacts in a semiconductor device
#22 | 2012-06-28Enhancement of ultraviolet curing of tensile stress liner using reflective materials
#23 | 2012-06-21Semiconductor Device Comprising a Contact Structure with Reduced Parasitic Capacitance
#24 | 2012-02-02Increasing robustness of a dual stress liner approach in a semiconductor device by applying a wet chemistry
#25 | 2012-01-05Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal features
#26 | 2012-01-05Semiconductor device comprising through hole vias having a stress relaxation mechanism
#27 | 2012-01-05Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction
#28 | 2011-12-01Selective shrinkage of contact elements in a semiconductor device
#29 | 2011-07-26Method for forming a metal silicide having a lower potential for containing material defects
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