Inventor profile of:

Chun-Chen Chen

City:

Hsinchu

Country:

Taiwan

Published Applications:

17

Last publication date:

2025-11-13

Top Assignees for applications by Chun-Chen Chen

The entities that hold a legal rights for patent applications filed by inventor Chen Chun-Chen:

Recent patent applications by Chen Chun-Chen

Chun-Chen Chen from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-11-13
US20250351572A1
Electricity

INTEGRATED CIRCUIT DEVICE WITH IMPROVED LAYOUT

#2 | 2025-06-26
US20250209249A1
Physics

SYSTEMS AND METHODS FOR INTEGRATED CIRCUIT LAYOUT

#3 | 2024-01-18
US20240020451A1
Physics

Systems and methods for integrated circuit layout

#4 | 2022-11-10
US20220358277A1
Physics

System for designing semiconductor device

#5 | 2021-07-22
US20210224456A1
Physics

Systems and methods for integrated circuit layout

#6 | 2021-02-11
US20210039402A1
Performing operations; transporting

THERMAL PRINT HEAD ELEMENT, THERMAL PRINT HEAD MODULE AND MANUFACTURING METHOD OF THE THERMAL PRINT HEAD MODULE

#7 | 2021-01-07
US20210004517A1
Physics

Method of designing semiconductor device

#8 | 2021-01-07
US20210001640A1
Performing operations; transporting

THERMAL HEAD STRUCTURE CAPABLE OF IMPROVING PRINTING RESOLUTION AND MANUFACTURING METHOD THEREOF

#9 | 2020-11-12
US20200353759A1
Performing operations; transporting

METHOD FOR MANUFACTURING THERMAL PRINT HEAD STRUCTURE

#10 | 2020-08-25
US16538803
Performing operations; transporting

Printing device, thermal print head structure and method for manufacturing the thermal print head structure

#11 | 2020-06-11
US20200180327A1
Performing operations; transporting

Method for manufacturing thermal print head

#12 | 2020-05-14
US20200152617A1
Electricity

Pin modification for standard cells

#13 | 2020-04-30
US20200134125A1
Physics

Semiconductor device with filler cell region, method of generating layout diagram and system for same

#14 | 2019-08-29
US20190266309A1
Physics

Method of designing semiconductor device and system for implementing the method

#15 | 2019-08-29
US20190263097A1
Performing operations; transporting

GRAPHENE COMPOSITE FILM AND MANUFACTURING METHOD THEREOF

#16 | 2019-04-04
US20190103392A1
Electricity

Pin modification for standard cells

#17 | 2018-02-01
US20180032661A1
Physics

Systems and methods for generating a multiple patterning lithography compliant integrated circuit layout

InventorID:

2106635 ⎘