Inventor profile of:

Mahmut Sinangil

City:

Campbell, California

Country:

United States

Published Applications:

31

Last publication date:

2025-11-27

Top Assignees for applications by Mahmut Sinangil

The entities that hold a legal rights for patent applications filed by inventor Sinangil Mahmut:

Recent patent applications by Sinangil Mahmut

Mahmut Sinangil from Campbell, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-11-27
US20250366138A1
Electricity

BACK SIDE POWER SUPPLY INTERCONNECT ROUTING

#2 | 2025-07-24
US20250239299A1
Physics

Pre-Charging Bit Lines Through Charge-Sharing

#3 | 2025-06-26
US20250210073A1
Physics

SERIES OF PARALLEL SENSING OPERATIONS FOR MULTI-LEVEL CELLS

#4 | 2025-06-19
US20250201281A1
Physics

MEMORY DEVICES WITH BACKSIDE BOOST CAPACITOR AND METHODS FOR FORMING THE SAME

#5 | 2024-11-14
US20240379149A1
Physics

COMPUTE IN MEMORY SYSTEM

#6 | 2024-10-31
US20240363594A1
Electricity

VERTICAL INTERCONNECT STRUCTURES WITH INTEGRATED CIRCUITS

#7 | 2024-03-07
US20240079053A1
Physics

Pre-charging bit lines through charge-sharing

#8 | 2023-11-23
US20230377614A1
Physics

Series of parallel sensing operations for multi-level cells

#9 | 2023-11-23
US20230376273A1
Physics

BOOTH MULTIPLIER FOR COMPUTE-IN-MEMORY

#10 | 2023-10-05
US20230315389A1
Physics

COMPUTE-IN-MEMORY CELL

#11 | 2023-09-14
US20230290840A1
Electricity

BACK SIDE POWER SUPPLY INTERCONNECT ROUTING

#12 | 2023-08-31
US20230274769A1
Physics

Memory devices with backside boost capacitor and methods for forming the same

#13 | 2023-05-04
US20230133360A1
Physics

Compute-In-Memory-Based Floating-Point Processor

#14 | 2022-09-22
US20220302088A1
Electricity

Vertical interconnect structures with integrated circuits

#15 | 2022-08-18
US20220262424A1
Physics

Compute in memory system

#16 | 2022-04-28
US20220130435A1
Physics

Series of parallel sensing operations for multi-level cells

#17 | 2021-12-16
US20210390987A1
Physics

Series of parallel sensing operations for multi-level cells

#18 | 2021-05-27
US20210158854A1
Physics

Compute in memory system

#19 | 2021-02-18
US20210050053A1
Physics

Low voltage bit-cell

#20 | 2020-12-24
US20200402572A1
Physics

Pre-charging bit lines through charge-sharing

#21 | 2020-11-26
US20200372951A1
Physics

SRAM cell for interleaved wordline scheme

#22 | 2020-03-05
US20200075092A1
Physics

Memory read stability enhancement with short segmented bit line architecture

#23 | 2019-11-14
US20190348110A1
Physics

Pre-charging bit lines through charge-sharing

#24 | 2019-10-03
US20190304520A1
Physics

Bit line logic circuits and methods

#25 | 2019-08-01
US20190237134A1
Physics

SRAM cell for interleaved wordline scheme

#26 | 2019-04-11
US20190108874A1
Physics

Memory read stability enhancement with short segmented bit line architecture

#27 | 2019-03-28
US20190096476A1
Physics

Low voltage bit-cell

#28 | 2018-07-12
US20180197601A1
Physics

Memory read stability enhancement with short segmented bit line architecture

#29 | 2018-06-21
US20180174649A1
Physics

Pre-charging bit lines through charge-sharing

#30 | 2018-06-07
US20180158510A1
Physics

SRAM cell for interleaved wordline scheme

#31 | 2018-02-08
US20180040366A1
Physics

Pre-charging bit lines through charge-sharing

InventorID:

2113147 ⎘