Eagle, Idaho
United States
33
2021-12-30
The entities that hold a legal rights for patent applications filed by inventor Ryan Kevin J.:
Kevin J. Ryan from Eagle, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Hybrid memory device using different types of capacitors
#2 | 2019-07-11Hybrid memory device using different types of capacitors and operating method thereof
#3 | 2018-03-01Hybrid memory device using different types of capacitors
#4 | 2012-02-09Apparatus and methods for optically-coupled memory systems
#5 | 2011-03-03System and method for optimizing interconnections of memory devices in a multichip module
#6 | 2010-11-16System and method for optimizing interconnections of memory devices in a multichip module
#7 | 2010-02-04Apparatus and methods for optically-coupled memory systems
#8 | 2008-07-24Method and system for using dynamic random access memory as cache memory
#9 | 2008-07-03Apparatus and methods for optically-coupled memory systems
#10 | 2008-04-24Method of timing calibration using slower data rate pattern
#11 | 2007-03-08Method and system for using dynamic random access memory as cache memory
#12 | 2007-01-11Dram with hidden refresh
#13 | 2006-09-14System and method for optimizing interconnections of memory devices in a multichip module
#14 | 2006-05-25Synchronous DRAM with selectable internal prefetch size
#15 | 2006-01-19DRAM with hidden refresh
#16 | 2005-12-20Dual mode DDR SDRAM/SGRAM
#17 | 2005-11-03Apparatus and methods for optically-coupled memory systems
#18 | 2005-11-03Apparatus and methods for optically-coupled memory systems
#19 | 2005-11-03Apparatus and methods for optically-coupled memory systems
#20 | 2005-11-01Apparatus and methods for optically-coupled memory systems
#21 | 2005-10-20Memory device interface
#22 | 2005-10-20Apparatus and methods for optically-coupled memory systems
#23 | 2005-09-20Method and system for using dynamic random access memory as cache memory
#24 | 2005-09-15Method of timing calibration using slower data rate pattern
#25 | 2005-09-06DRAM with hidden refresh
#26 | 2005-06-14Memory device interface
#27 | 2005-05-17Synchronous DRAM with selectable internal prefetch size
#28 | 2005-04-21Synchronous DRAM with selectable internal prefetch size
#29 | 2005-04-21Method for selecting memory device in response to bank selection signal
#30 | 2005-03-01Method and system for using dynamic random access memory as cache memory
#31 | 2005-02-01System latency levelization for read data
#32 | 2005-01-18Device and system for adjusting delay in a data path based on comparison of data from a latch and data from a register
#33 | 2005-01-11Method for selecting one or a bank of memory devices
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