Inventor profile of:

Ruby B. Lee

City:

Princeton, New Jersey

Country:

United States

Published Applications:

29

Last publication date:

2026-03-26

Top Assignees for applications by Ruby B. Lee

The entities that hold a legal rights for patent applications filed by inventor Lee Ruby B.:

Recent patent applications by Lee Ruby B.

Ruby B. Lee from Princeton, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-03-26
US20260086955A1
Physics

RANDOMIZED AND SAFE CACHE ARCHITECTURE

#2 | 2024-12-05
US20240403220A1
Physics

Systems and Methods for Random Fill Caching and Prefetching for Secure Cache Memories

#3 | 2021-11-25
US20210365590A1
Physics

Systems and methods for random fill caching and prefetching for secure cache memories

#4 | 2021-03-18
US20210084075A1
Electricity

System and method for security health monitoring and attestation of virtual machines in cloud computing systems

#5 | 2020-09-17
US20200293657A1
Physics

Anomalous behavior detection in processor based systems

#6 | 2019-06-06
US20190171476A1
Physics

System and method for self-protecting data

#7 | 2018-02-15
US20180045189A1
Mechanical engineering

System and method for processor-based security

#8 | 2017-08-10
US20170227995A1
Physics

METHOD AND SYSTEM FOR IMPLICIT AUTHENTICATION

#9 | 2016-12-15
US20160366185A1
Electricity

System and method for security health monitoring and attestation of virtual machines in cloud computing systems

#10 | 2016-08-25
US20160246736A1
Physics

System and method for processor-based security

#11 | 2016-06-16
US20160170889A1
Physics

Systems and methods for random fill caching and prefetching for secure cache memories

#12 | 2015-12-10
US20150356026A1
Physics

Cache memory having enhanced performance and security features

#13 | 2015-02-26
US20150058997A1
Physics

System and method for self-protecting data

#14 | 2014-04-03
US20140095797A1
Physics

Cache memory having enhanced performance and security features

#15 | 2013-04-25
US20130103730A1
Physics

Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor

#16 | 2010-11-04
US20100281273A1
Mechanical engineering

System and method for processor-based security

#17 | 2010-09-09
US20100228939A1
Physics

Parallel read functional unit for microprocessors

#18 | 2010-07-15
US20100180083A1
Physics

Cache memory having enhanced performance and security features

#19 | 2010-02-18
US20100042824A1
Physics

Hardware trust anchors in SP-enabled processors

#20 | 2009-05-28
US20090138534A1
Physics

Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor

#21 | 2008-09-09
US10403785
-

Variable reordering (Mux) instructions for parallel table lookups from registers

#22 | 2007-09-25
US10403754
-

Image matching using pixel-depth reduction before image comparison

#23 | 2007-02-06
US9850239
-

Method and system for performing permutations with bit permutation instructions

#24 | 2006-08-15
US9850380
-

Method and system for performing subword permutation instructions for use in two-dimensional multimedia processing

#25 | 2006-02-23
US20060039555A1
Physics

Method and system for performing permutations using permutation instructions based on butterfly networks

#26 | 2005-10-04
US9850238
-

Method and system for performing permutations using permutation instructions based on modified omega and flip stages

#27 | 2005-08-11
US20050177706A1
Physics

Parallel subword instructions for directing results to selected subword locations of data processor result register

#28 | 2005-07-26
US9850237
-

Method and system for performing permutations using permutation instructions based on butterfly networks

#29 | 2005-07-07
US20050149590A1
Physics

Method and system for performing permutations with bit permutation instructions

InventorID:

213690 ⎘