San Jose, California
United States
55
2017-03-16
The entities that hold a legal rights for patent applications filed by inventor Weber Frederick Daniel:
Frederick Daniel Weber from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Configurable memory circuit system and method
#2 | 2016-02-18Configurable memory circuit system and method
#3 | 2015-03-10Hybrid memory module
#4 | 2014-07-10Configurable memory circuit system and method
#5 | 2013-07-25Simulating a memory standard
#6 | 2013-07-25SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION
#7 | 2013-04-25Translating an address associated with a command communicated between a system and memory circuits
#8 | 2013-04-25Memory module with memory stack and interface with enhanced capabilites
#9 | 2013-03-12Hybrid memory module
#10 | 2012-09-06Performing power management operations
#11 | 2012-08-09Memory circuit system and method
#12 | 2012-06-14Memory refresh apparatus and method
#13 | 2012-05-03System and Method for Simulating an Aspect of a Memory Circuit
#14 | 2012-04-26Memory module with memory stack and interface with enhanced capabilities
#15 | 2012-01-12Memory apparatus operable to perform a power-saving operation
#16 | 2012-01-12Simulating a memory standard
#17 | 2012-01-12Simulating a refresh operation latency
#18 | 2010-11-04Performing power management operations
#19 | 2010-10-28Delaying a signal communicated from a system to at least one of a plurality of memory circuits
#20 | 2009-11-19Simulating a memory circuit
#21 | 2009-01-22Memory circuit system and method
#22 | 2009-01-22Memory circuit system and method
#23 | 2008-10-02Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
#24 | 2008-10-02Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
#25 | 2008-06-05Apparatus for simulating an aspect of a memory circuit
#26 | 2008-05-29Memory apparatus operable to perform a power-saving operation
#27 | 2008-05-29Memory module with memory stack
#28 | 2008-05-29MEMORY DEVICE WITH EMULATED CHARACTERISTICS
#29 | 2008-05-29MEMORY DEVICE WITH EMULATED CHARACTERISTICS
#30 | 2008-05-29MEMORY DEVICE WITH EMULATED CHARACTERISTICS
#31 | 2008-05-29Combined signal delay and power saving for use with a plurality of memory circuits
#32 | 2008-05-22System and method for reducing command scheduling constraints of memory circuits
#33 | 2008-05-08SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS
#34 | 2008-05-08MEMORY DEVICE WITH EMULATED CHARACTERISTICS
#35 | 2008-05-01MEMORY DEVICE WITH EMULATED CHARACTERISTICS
#36 | 2008-05-01MEMORY DEVICE WITH EMULATED CHARACTERISTICS
#37 | 2008-03-13System and method for simulating an aspect of a memory circuit
#38 | 2008-03-06Memory device with emulated characteristics
#39 | 2008-02-14Interface circuit system and method for performing power saving operations during a command-related latency
#40 | 2008-02-07Power saving system and method for use with a plurality of memory circuits
#41 | 2008-02-07System and method for power management in memory systems
#42 | 2008-01-31MULTIPLE-COMPONENT MEMORY INTERFACE SYSTEM AND METHOD
#43 | 2008-01-31Memory circuit simulation system and method with refresh capabilities
#44 | 2008-01-31Simulating a different number of memory circuit devices
#45 | 2008-01-31Memory circuit simulation with power saving capabilities
#46 | 2008-01-31System and method for simulating an aspect of a memory circuit
#47 | 2008-01-31SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION
#48 | 2008-01-31Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
#49 | 2008-01-31Interface circuit system and method for performing power management operations utilizing power management signals
#50 | 2008-01-31Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
#51 | 2008-01-31Memory refresh apparatus and method
#52 | 2008-01-31System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
#53 | 2007-08-30System and method for reducing command scheduling constraints of memory circuits
#54 | 2007-08-23Memory module with memory stack and interface with enhanced capabilities
#55 | 2007-08-16Translating an address associated with a command communicated between a system and memory circuits
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