Peekskill, New York
United States
40
2017-09-14
The entities that hold a legal rights for patent applications filed by inventor Krishnan Siddarth A.:
Siddarth A. Krishnan from Peekskill, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor
#2 | 2017-07-20Structures with thinned dielectric material
#3 | 2017-04-20Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor
#4 | 2017-01-17Method and structure for III-V nanowire tunnel FETs
#5 | 2016-12-15Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
#6 | 2016-10-20Replacement channel TFET
#7 | 2016-08-18Modified tungsten silicon
#8 | 2016-03-24Constrained nanosecond laser anneal of metal interconnect structures
#9 | 2016-01-28Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme
#10 | 2016-01-07Field effect transistors having multiple effective work functions
#11 | 2015-12-03Variable length multi-channel replacement metal gate including silicon hard mask
#12 | 2015-05-28Variable length multi-channel replacement metal gate including silicon hard mask
#13 | 2015-03-12Semiconductor devices having different gate oxide thicknesses
#14 | 2015-02-12Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches
#15 | 2015-01-22FIN Field Effect Transistors Having Multiple Threshold Voltages
#16 | 2015-01-22Intrinsic Channel Planar Field Effect Transistors Having Multiple Threshold Voltages
#17 | 2014-07-03Concurrently forming nFET and pFET gate dielectric layers
#18 | 2014-06-19Structure and method of Tscaling for high k metal gate technology
#19 | 2014-03-06Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices
#20 | 2014-02-27Non-volatile memory structure employing high-k gate dielectric and metal gate
#21 | 2014-01-02Semiconductor devices having different gate oxide thicknesses
#22 | 2013-10-24ETCH STOP LAYER FORMATION IN METAL GATE PROCESS
#23 | 2013-10-24Etch stop layer formation in metal gate process
#24 | 2013-08-22Replacement gate with reduced gate leakage current
#25 | 2013-08-01Replacement metal gate structures providing independent control on work function and gate leakage current
#26 | 2013-07-25Structure and method of Tscaling for high k metal gate technology
#27 | 2013-07-11Thermally stable high-K tetragonal HFOlayer within high aspect ratio deep trenches
#28 | 2013-05-23Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices
#29 | 2013-05-02Non-volatile memory structure employing high-k gate dielectric and metal gate
#30 | 2012-07-19Replacement gate with reduced gate leakage current
#31 | 2012-07-19Structure and method of Tscaling for high Îș metal gate technology
#32 | 2012-06-07Replacement gate devices with barrier metal for simultaneous processing
#33 | 2012-05-31Replacement metal gate structures providing independent control on work function and gate leakage current
#34 | 2011-11-03Method to optimize work function in complementary metal oxide semiconductor (CMOS) structures
#35 | 2011-05-26Gate effective-workfunction modification for CMOS
#36 | 2010-09-30METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS
#37 | 2010-07-29Semiconductor device having dual metal gates and method of manufacture
#38 | 2010-04-06Method of forming gate stack and structure thereof
#39 | 2009-08-27Gate effective-workfunction modification for CMOS
#40 | 2009-03-03Nitrogen based plasma process for metal gate MOS device
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