Edward O. Travis

Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures

Teleconferencing environment having auditory and visual cues

Integrated circuit design using pre-marked circuit element object library

Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit

Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures

Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device

SEMICONDUCTOR MANUFACTURING USING DESIGN VERIFICATION WITH MARKERS

Thin beam deposited fuse

3D device packaging using through-substrate posts

3D device packaging using through-substrate pillars

3D device packaging using through-substrate posts

Stress migration mitigation

Capping layer interface interruption for stress migration mitigation

Method for forming an electrical connection between metal layers

Fuse/resistor utilizing interconnect and vias and method of making

Semiconductor device with embedded heat spreading

Semiconductor device with vias on a bridge connecting two buses

Multi-layer process-induced damage tracking and remediation

Method for forming an integrated circuit having a programmable fuse

Method for forming an electrical connection between metal layers

Method and system for derived layer checking for semiconductor device design

Method for forming an electrical connection between metal layers

Method for forming an electrical connection between metal layers

Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules

Device matching tool and methods thereof

Via placement and electronic circuit design processing method and electronic circuit design utilizing same

Mismatch verification device and methods thereof

Semiconductor device with embedded heat spreading

Semiconductor device with heat dissipation

Method of protecting against via failure and structure therefor

Semiconductor device with vias on a bridge connecting two buses

Integrated assist features for epitaxial growth

Method and apparatus for indicating directionality in integrated circuit manufacturing

Electronic device including a capacitor and a process of forming the same

Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation

Integrated assist features for epitaxial growth bulk tiles with compensation

Integrated assist features for epitaxial growth

Integrated assist features for epitaxial growth

Primitive cell method for front end physical design

Die level metal density gradient for improved flip chip package reliability

Method and apparatus for indicating directionality in integrated circuit manufacturing

EPI T-gate structure for CoSiextendibility

Spacer T-gate structure for CoSiextendibility

Method of implementing polishing uniformity and modifying layout data

Integrated circuit having structural support for a flip-chip interconnect pad and method therefor

Semiconductor device for reducing photovolatic current

Method of implementing polishing uniformity and modifying layout data

Semiconductor device for reducing photovolatic current