Edward M. McCombs

System Control Using Sparse Data

System Control Using Sparse Data

System control using sparse data

System control using sparse data

System control using sparse data

Low active power write driver with reduced-power boost circuit

System control using sparse data

Low active power write driver with reduced-power boost circuit

MEMORY ARRAY POWER REDUCTION THROUGH REDUCED SUPPLY VOLTAGE

Integrated circuit power reduction through charge

Weak bit detection using on-die voltage modulation

Variable pre-charge levels for improved cell stability

METHOD FOR OPTIMIZING SENSE AMPLIFIER TIMING

Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation

Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation

Mechanism for peak power management in a memory

Memory with a shared I/O including an output data latch having an integrated clamp

MEMORY DEVICE INCLUDING A RETENTION VOLTAGE RESISTOR

Memory including a reduced leakage wordline driver

Integrated circuit including pulse control logic having shared gating control

Power estimation in an integrated circuit design flow

Scannable flip-flop with hold time improvements

Translation Lookaside Buffer Structure Including a Data Array Having an Integrated Multiplexer

Translation lookaside buffer structure including an output comparator

Translation Lookaside Buffer Structure Including a Data Array Storing an Address Selection Signal

Translation Lookaside Buffer Structure Including a Data Array Sense Amplifier and Fast Compare Unit

Integrated circuit including pulse control logic having shared gating control